1. Consider depletion-loaded NMOS with V DD = 5 V, V TO = 0.5 V, V TL = –0.6 V, and t ox = 18 nm. All devices have 0.5 mm gate lengths. Choose the W O /W L ratio such that V OL = 25 mV. 2. Consider...

1. Consider depletion-loaded NMOS with V_DD
= 5 V, V_TO
= 0.5 V, V_TL
= –0.6 V, and t_ox
= 18 nm. All devices have 0.5 mm gate lengths. Choose the W_O/W_L
ratio such that V_OL
= 25 mV.

2. Consider depletion-loaded NMOS with V_DD
= 3.3 V, V_TO
= 0.5 V, V_TL
= –0.3 V, and t_ox
= 10 nm. All devices have 0.35 mm gate lengths. Design the transistors for the inverter (choose W_O
and W_L) such that V_OL
= 20 mV and the average DC dissipation is 2 mW.