1. If the CPU of Exercise 7 had a two-way set-associative cache, again with 256 eight-byte cache lines, how many bits would be required for each cache entry? 2. For Figure 12.30, (a) draw the...

cache lines, how many bits would be required for each cache entry?

2.
For Figure 12.30,
(a)
draw the implementation of a comparator, the circle with the equals

sign. (Hint:
Consider the truth table of an XOR followed by an inverter, sometimes called an

XNOR gate.)
(b)
Draw the input and output connections to and from the 128 four-input

multiplexers.
(c)
Draw the implementation of one of the 128 four-input multiplexers. You

may use ellipses (. . .) in parts (a) and (b) of the exercise.