A 4 bit (Q3 Q₂ Q₁ Qo) binary down ripple counter is designed. The clock cycles are negative edge triggered and J-K-Flip-Flops (FF's) are used during the design process. Both the inputs J and K of FF's...

A 4 bit (Q3 Q₂ Q₁ Qo) binary down ripple counter is designed. The clock cycles are negative edge triggered and J-K-Flip-Flops (FF's) are used during the design process. Both the inputs J and K of FF's are connected to logic 1. What will be the input to clocks of next MSB FF's?