Assume the second stage of the S/H of Fig XXXXXXXXXXhas a gain of –30 and a unity-gain frequency of 100 MHz. Also assume the input signal is a 5-MHz sinusoid with a 2 Vp-p amplitude and the clock...

Assume the second stage of the S/H of Fig. 11.10 has a gain of –30 and a unity-gain frequency of 100 MHz. Also assume the input signal is a 5-MHz sinusoid with a 2 Vp-p amplitude and the clock signals are at 20 MHz and go between +2.5 V and –2.5 V, with rise and fall times of 1.5 ns. What is the sampling time uncertainty?