Cache coherence protocol. Consider a cache coherence protocol in which each cache line can be in one of three states on each processor:invalid (this processor doesn’t have a copy), shared (this...

Cache coherence protocol. Consider a cache coherence protocol in which each cache line can be in one of three states on each processor:invalid (this processor doesn’t have a copy), shared (this processor has a read-only copy), and exclusive (this processor has an exclusive copy that may be dirty). Describe the sequence of messages that must be sent to handle a read or a write to a cache line in each of the possible states.