Computer Architecture Assignment RISC-V Greencard: https://inst.eecs.berkeley.edu/~cs61c/fa17/img/riscvcard.pdf Question 3 One advantage of Processor C to make up for its performance in comparison to...

Computer Architecture Assignment
RISC-V Greencard: https://inst.eecs.berkeley.edu/~cs61c/fa17/img/riscvcard.pdf
Question 3
One advantage of Processor C to make up for its performance in comparison to other processors is the size of the register files. Processor C has the capability to handle 256-bit numbers in the register file for simpler work with cryptographic processes or larger files. If our design is going to be monitoring buildings for door openings and environmental conditions, you are probably going to want to encrypt some amount of data to ensure that someone can’t casually see when someone is there.
Assume that your code needs to run this type of cryptographic process, thus, you will need to support 256-bit numbers. However, you know that for the types of processes you need to support, you can break up those numbers into 64-bit numbers.
Also, assume that for all processors, the register file is 32 registers long, HOWEVER, since these are all RISC-V processors, they follow the standard convention for register usage, meaning that each register has a purpose as seen below in the table from the RISC-V greencard.
Assume that these values have already been pulled into the register file and can only be stored in the “Temporary” registers (t0 – t6) and the Function Argument registers (a0-a7).
For each of the processors, determine the amount of 256-bit variables/values which can be stored for instruction execution.
Processor A
(64-bit Architecture)
Processor B
(64-bit Architecture)
Processor C
(256-bit Architecture)



Question 4
Processor C costs more to purchase for the design versus the other processors, partly due to the 256-bit architecture.
Provide a short discussion (3-4 sentences) as to the impacts which increasing your architecture size (from 64 to 256) has on the design of the processor as whole, not just that the register file will be bigger.
Mandatory Extra Credit (will count as one question)
You must attempt this question in some capacity; however, any points greater than 0 on this question will be used as extra credit in the exam.
If you noticed that in Question 3 when talking about the function arguments and return values, this is referring to the idea of functions in code, such as:
myFunction( input 1, input 2)

return result;
Remember that functions are stored in your program just like everything else, and are typically branched/jumped to, meaning that you will need to get your register file prepared with values before entering the function.
There is an extremely important realization that need to happen when dealing with any processor, and that is the register file is in fact a finite size. So for example, looking at the comparison you did in Question 3, Processors A and B could handle far fewer arguments than 256-bit Processor C. While this question extends to every processor and architecture, let’s take a look at Processor A and B.
For Processor A and B, what if I had a function which needed to take in 10, 256-bit arguments and then return a single 256-bit argument. Based on the Greencard, the following registers are available for usage with functions:
x10 – x11: Function Arguments / Return Values (note that return values only are here)
x12 – x17: Function Arguments
There is a problem here, since there are only up to 2 registers for return values and up to 8 registers for function arguments, and we are dealing with 256-bit numbers, nothing is going to fit directly.
Knowing that you have access to data memory where these values are stored ( Mem[n] ), determine a strategy for facilitating this type of function and provide a rough RISC-V Instruction example for how you plan to access all of these values.
MAJOR HINT: If you can think back to programming courses, there were times where you wanted to deal with pointers. I wonder why there is support for pointers to memory locations in high level code?
Question 5
From here on out, we are going to be talking about Processor A and Processor B which are 64-bit architectures. Each of these processors have the same datapath and control signals, as seen below.
For the following sequence of instructions, for the INSTRUCTIONS WHICH ARE HIGHLIGHTED determine the control signals for each of the instructions and the values of the busses indicated.
Instruction Sequence:
add x5 x0 x0
sub x6 x0 x0
addi x7 x0 1
addi x28 x0 1000 // decimal
addi x29 x0 100 // decimal
bge x7 x28 7
add x5 x6 x0
add x6 x7 x0
add x7 x5 x6
addi x29 x29 1
sd Mem[x29] x7 0
jal x31 -6
jal x31 -12
For any unknown, use don’t cares (x)
sub x6 x0 x0
bge x7 x28 7
Assume x7 < x28
sd Mem[x29] x7 0
Assume x29 = 100
jal x31 -6
RegWrite (0, 1)




ALUSrc (0, 1)




ALUOp (00-11)




MemWrite (0,1)




MemRead (0,1)




MemToReg (0,1)




PCSrc (0,1)




A (binary)




B (binary)




C (binary)




D (xN)




E (xN, Mem[n])




F (PC + N)




Question 6
First, determine the function of the instruction sequence in Question 5. It actually does something meaningful, it isn’t just random.
Hint: To approach this, I would just write down what is happening through the sequence and see if you can determine any sort of behaviors or patterns from there.
Next, you saw that the instructions had a branching condition, but I want to determine how you would write the RISC-V instruction sequence for the following conditional statement.
if X > N
Assume:
X x30
N x31
You only need to determine the proper branch/jump instruction.
Question 7
Processor B has a pipelined datapath which already has hazard detection and a forwarding unit.
Determine the sequence in which the following instructions from Question 5 and 6 will operate. The table provided may have more rows and columns than required. You will need to determine which instruction is running on the rows going in order (inserting any NOPs the hazard detection unit might assert), and place the stage where the instruction is located (IF, ID, EX, MEM, WB). If a NOP is inserted from the hazard detection unit, it can be represented by writing NOP in the instruction column and the showing the delay in future instructions.
add x5 x6 x0
add x6 x7 x0
add x7 x5 x6
addi x29 x29 1
sd Mem[x29] x7 0
Instruction
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
CC9
CC10
CC12
CC13
CC14






























































































































Question 8
Assume all of the processors have a GPIO peripheral for interfacing with our Door Opening Sensors and an Analog to Digital Converter for reading from the temperature and humidity sensors. A simplified tabled of what the special function registers are and what they do are located below. All memory locations are in Data Memory of the datapath.
Abbreviation
Name
Memory Location
Purpose
P1DIR
Port 1 Pin Direction
0xFFFFEE00
Direction of signal flow for the pin:
0x00: Input
0x01: Output
P1IE
Port 1 Interrupt Enable
0xFFFFEE01
Enable the Port to Interrupt the Processor when a pin changes state:
0x00: Disable Interrupts
0x01: Enable Interrupts
P1OUT
Port 1 Pin Output
0xFFFFEE02
Set the state of a pin:
0x00: Output logic 0
0x01: Output logic 1
P1IN
Port 1 Input
0xFFFFEE03
Current state of input pin. (set by peripheral)
P2DIR
Port 2 Pin Direction
0xFFFFEE04
Direction of signal flow for the pin:
0x00: Input
0x01: Output
P2IE
Port 2 Interrupt Enable
0xFFFFEE05
Enable the Port to Interrupt the Processor when a pin changes state:
0x00: Disable Interrupts
0x01: Enable Interrupts
P2OUT
Port 2 Pin Output
0xFFFFEE06
Set the state of a pin:
0x00: Output logic 0
0x01: Output logic 1
P2IN
Port 2 Input
0xFFFFEE07
Current state of input pin. (set by peripheral)
ADC10MODE
ADC10 Current Mode
0xFFFFEE10
Set the mode of the ADC10:
0x00: Stop
0x01: Single Sample (run once, then wait for ADC10START to run again)
0x02: Continuous Sample
ADC10START
ADC10 Starting Trigger
0xFFFFEE11
When set to 1, triggers a reading, then peripheral sets back to 0
ADC10VAL
ADC10 Current Value
0xFFFFEE12
Current value of the ADC10, set by the peripheral
Assume that when our processor resets/starts up, all of these registers are set to 0.
We want our processor to run the following pseudocode sequence as its main routine (purpose in life).
Configure Peripherals
Set Port 1 to an output
Set Port 2 to an input
Enable Interrupts on Port 2
Set ADC10 to Single Sample Mode
Measurement Loop
Tell ADC to take a measurement
If Port 2 is switched on (Logic 1)
Check ADC10 to see if value read is above 255
If it is over 255
Set Port 1 to a Logic 1 (Turn on the LED)
If not over 255
Set Port 1 to a Logic 0 (Turn off the LED)
Come up with a RISC-V Assembly Implementation of the following parts of this sequence. Assume that we are starting from a RESET, meaning all registers are cleared to a 0.
Set Port 1 to an Output:
Set Port 2 to an Input:
Enable Interrupts on Port 2:
Set ADC10 to Single Sample Mode:
Establish an infinite loop (just give the beginning and end instructions, assume this is instruction number 10):
Make the ADC take a measurement:
If Port 2 is Switched On (Give the instruction, leave the offset empty):
Check ADC10 to see if value is above 255 (Give instructions to read and the conditional):
Set Port 1 to a Logic 1:
Question 9
Using the instructions from Question 8 and the provided C based version of the code, create the RISC-V instruction sequence to run the main routine as seen in Question 8.
Hint: Start out by listing the instructions in order, then you can determine any of the branching or jumping that is needed.
C implementation:
P1DIR = 0x01;
P2DIR = 0x00; // Ensure it is set as an output
P2IE = 0x01;
ADC10MODE = 0x01;
while(1)
{
ADC10START = 0x01;
If (ADC10VAL >= 255)
P1OUT = 0x01;
else if (ADC10VAL < 255)
P1OUT = 0x00;
}
May 09, 2021

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