Virtualization(X86 & ARM) and O/S X. __________ True/False : Prior to the introduction of Intel VMX/AMD SVM, it was not possible to fully virtualize a guest OS on the x86 platform. X. __________ Which...

Computer Virtualization(X86 & ARM) and O/S Quiz


Virtualization(X86 & ARM) and O/S X. __________ True/False : Prior to the introduction of Intel VMX/AMD SVM, it was not possible to fully virtualize a guest OS on the x86 platform. X. __________ Which of the following is a feature provided by a VMM? A. Scheduling VCPUs on PCPUs B. Scheduling processes on CPUs C. Handling system calls from processes D. All of the above E. None of the above X. __________ Which of the following terms describes a possible treatment of floating point registers during a process context switch? A. MOV to CR3 B. Lazy switch C. Page fault D. FPU E. None of the above X. __________ Which of the following best describes the size of the virtual address space on 32-bit Intel CPUs? A. Always 32 bits B. Always more than 32 bits C. Sometimes more than 32 bits, depending on the CPU D. None of the above X. __________ Which of the following best describes the size of the physical address space on 32-bit Intel CPUs? A. Always 32 bits B. Always more than 32 bits C. Sometimes more than 32 bits, depending on the CPU D. None of the above X. __________ When operating in 32 bit mode, the depth of the processor's paging structures (page directory/page table) is: A. 2 levels deep B. 3 levels deep C. 4 levels deep D. There is not enough information provided to answer the question accurately X. __________ When operating in 64 bit (long) mode, the depth of the processor's paging structures (page directory/page table) is: A. 2 levels deep B. 3 levels deep C. 4 levels deep D. There is not enough information provided to answer question accurately X. __________ True/False: A legacy system BIOS is typically responsible for selecting a boot device from amongst the available boot devices (perhaps with input from the end user). X. __________ True/False: The x86 architecture provides for four privilege levels of operation. X. __________ Which of the following contains mappings between interrupt vector numbers and interrupt handler routines? A. IDT B. LDT C. GDT D. SDT E. None of the above X. __________ Which of the following will occur if “exit on HLT” is disabled and a guest OS executes the HLT instruction, when running on a multiprocessor machine? A. The VCPU will become unresponsive until a virtual interrupt is delivered B. The PCPU will become unresponsive until a physical interrupt is delivered C. The hypervisor will be unable to schedule other VCPUs on the PCPU that is halted D. All of A,B, and C E. None of A,B, or C X. __________ Which world switch consumes more CPU processing time during register read/write to/from the VMCS? A. VM Entry B. VM Exit C. Both VM Entries and VM Exits take equal time