Consider CMOS circuitry driving a 50-pF off-chip load as shown in Figure 9.73. t ox = 16 nm. V T = 0.5 V. Suppose that each successive stage is scaled up in current driving capability by a factor of...

Consider CMOS circuitry driving a 50-pF off-chip load as shown in Figure 9.73. t_ox
= 16 nm. V_T
= 0.5 V. Suppose that each successive stage is scaled up in current driving capability by a factor of 3.

1. Determine the required number of buffer stages such that t_P
≤ 0.6 ns.

2. Use SPICE to verify your design.

Figure 9.73