Consider depletion-loaded NMOS with V DD = 3.3 V, V TO = 0.5 V, V TL = –0.3 V, and t ox = 10 nm. All devices have 0.35 mm gate lengths. Design the transistors for the inverter (choose WO and WL) such...

Consider depletion-loaded NMOS with V_DD
= 3.3 V, V_TO
= 0.5 V, V_TL
= –0.3 V, and t_ox
= 10 nm. All devices have 0.35 mm gate lengths. Design the transistors for the inverter (choose WO and WL) such that V_OL
= 20 mV and t_P
≤ 10 ns with C_L
= 15 pF. (Consider the worst-case propagation delay.)