Consider depletion-loaded NMOS with V DD = 3.3 V, V TO = 0.5 V, V TL = –0.3V, and t ox = 9 nm. All devices have 0.3 mm gate lengths. Is it possible to design the transistors for the inverter such that...

Consider depletion-loaded NMOS with V_DD
= 3.3 V, V_TO
= 0.5 V, V_TL
= –0.3V, and t_ox
= 9 nm. All devices have 0.3 mm gate lengths. Is it possible to design the transistors for the inverter such that VOL = 20 mV, tP_LH
≤ 10 ns with C_L
= 15 pF and P_DC
£ 1 mW? Provide a design satisfying these requirements or show why one does not exist.