Consider DVS implemented in 0.25-μm CMOS technology with t OX = 7 nm. A ring oscillator is designed to mimic the critical path in the system using 13 stages of symmetric inverters with load...

Consider DVS implemented in 0.25-μm CMOS technology with t_OX
= 7 nm. A ring oscillator is designed to mimic the critical path in the system using 13 stages of symmetric inverters with load capacitances at each stage equivalent to 15 on-chip loads.

1. Calculate and plot the ring oscillator frequency as a function of the supply voltage assuming VT = 0.3 V for all devices. 1 V ≤ V_DD
≤ 5 V

2. Calculate and plot the switching power vs. the supply voltage for a symmetric inverter in the system. Assume the system clock frequency is derived from the ring oscillator, the switching activity is 0.2, and the on-chip fan-out is 15. For the symmetric inverter, W_N
= 1 μm.