Consider the SSL/TLS hardware accelerator (see Section XXXXXXXXXXthat is required to generate a 128-bit random key at a speed of 1 Gbps (system clock speed). However, the hardware TRNG inside it...

Consider the SSL/TLS hardware accelerator (see Section 12.4.4) that is required to generate a 128-bit random key at a speed of 1 Gbps (system clock speed). However, the hardware TRNG inside it produces raw true random bits at a 1000x slower speed. Provide a scheme that can produce random output at a required speed. For simplicity, you can assume the key-bits are generated in parallel.