Consider the standard TTL inverter of Figure XXXXXXXXXXAll transistors and diodes may be scaled in geometrical size with a direct effect on the parasitic capacitances C JDO , C JEO , and C JCO as...

Consider the standard TTL inverter of Figure 5.100. All transistors and diodes may be scaled in geometrical size with a direct effect on the parasitic capacitances C_JDO, C_JEO, and C_JCO
as shown in the figure.

1. Using SPICE, determine and plot t_PLH
vs. x.

2. Using SPICE, determine and plot t_PHL
vs. x.

3. Determine and plot the power delay product vs. x.

Figure 5.100