file attached
CS3339 CS3339 Assignment 2 10-15-2021 Due 10-26-2021 Submission Instructions: Please, carefully, follow the submission instructions provided in assignment 1. Assignment Instructions: 1) Please map the instructions into the numbered version of figure 4.51, attached below, using only figure 4.5.1 and carefully following the way that microinstructions are flowing through diagram registers (e.g., forwarding of I2 to I6). You can only use diagram 4.5.1 (do not use the single cycle diagram – it is attached only for reference) 2) Trace the micro execution of each microinstruction of each instruction according to the sequence of microinstructions developed in class and in assignment2. An example of a microinstruction trace for the ADD and BEQ instruction will be given in class on 4/19/2021. 3) For your answers, please use the format presented in the lectures 4) Assume that the instructions are executed in sequence and that the compiler/assembler/loader/machine do not check for errors. 5) For each instruction you have to provide the general syntax, type, global semantics, micro- instructions, and a trace of the result of IF, ID, EX, Mem, and WB. 6) show the contents of relevant Registers / I registers (e.g., I2) and control lines before and after the execution of each microinstruction. You can use class notes and the solution for Assignment 2 with the proper explanation. 7) Note that you might need to add hardware for the JAL, BNE, and JR. Initial conditions: $RA=1900; { $v0,$a0, $a1,$s0,$s1,$s2,Ss3,$sp} = {5, 10, 15, 20, 25,30,35,1000} 0x12341234 start: sw $v0, 500($ra) // bne $a0, $a1, endLoop1 //convert to real instructions ori $s0, $s0, 1 xor $s3, $s1, $s2 jal start endloop1: jr $sp Legend for numbered figure 4.51 I4 – IR I8 – Register A – storing RD1 I10 – Register B – storing RD2 I12 – Register C – storing SE[IR[15-0]] // SE stands for sign extension I18 - Add_Result I24 – Zero_Flag I26 – ALU_result I32 – Read_Data_Memory CS3339 Assignment 2 10-15-2021 Due 10-26-2021 36 CS3339 Assignment 2 10-15-2021 Due 10-26-2021 The Single Cycle Diagram with a mechanism for jump 10/19/2021 Addi Addi $22, $23, 1025 $22 $23 + 1025 Assume the instruction is stored in address 1000 decimal Trace IF I4 IM[PC] ; I4 = 001000 10111 10110 0000 0010 0000 0001 //??? I2 PC + 4 ; I2 = 1004 ID CLU IR[31-26] || IR[5-0] // Addi CLU 001000, 0000001 RR1 IR[25-21] // 23 (&23) RR2 IR[20-16] // jnk I8 * $23 // Either given or assumed by you DT assume 8 I10 jnk I6 I2 : I6 = 1004 I12 SE[IR[15-0]] constant in instruction Such as addi // I12 = 0000 0000 0000 0000 0000 0010 0000 0001 I14 &$rt // I14 = 23 I16 &$rd // jnk I26 I8 + I12 // I26 = 0000 0000 0000 0000 0000 0010 0000 0009 I30 I14 // I30 = 23 AluSrc 1 // to get I12 as the second input to the ALU. RegDst 0 //select $rt for the WB ALUContol 00 I32 // N/A I34 I26 (ALU result) // I34 = 0000 0000 0000 0000 0000 0010 0000 0009 I36 I30 // I30 = 23 Write Register I36 = 23 Write Data I34 = 0000 0000 0000 0000 0000 0010 0000 0009 I36 I30 // I30 = 23 // I assume that writing back to PC is done at the WB stage of the addi MemToReg 0 RegWrite 1 PCSrc 0 // PC PC + 4 // PC = 10034 IF I4 IM[PC] ; I4 = 001000 10111 10110 0000 0010 0000 0001 //??? I2 PC + 4 ; I2 = 1004 CLU IR[31-26] || IR[5-0] // Addi CLU 001000, 0000001 RR1 IR[25-21] // 23 (&23) RR2 IR[20-16] // jnk I8 * $23 // Either given or assumed by you DT assume 8 I10 jnk I6 I2 : I6 = 1004 I12 SE[IR[15-0]] constant in instruction Such as addi // I12 = 0000 0000 0000 0000 0000 0010 0000 0001 I14 &$rt // I14 = 23 I16 &$rd // jnk I26 I8 + I12 // I26 = 0000 0000 0000 0000 0000 0010 0000 0009 I30 I14 // I30 = 23 I34 I26 (ALU result) // I34 = 0000 0000 0000 0000 0000 0010 0000 0009 I36 I30 // I30 = 23 Write Register I36 = 23 Write Data I34 = 0000 0000 0000 0000 0000 0010 0000 0009 I36 I30 // I30 = 23 PC PC + 4 // PC = 10034 MIPS Pipeline Five Stages 4-33 35 - 3 consecutive LW going through the pieline. 41 another format for representing instruction flow through the pipeline 2 instructions + forwarding (ignore for now). Pipeline hazards Slide 38, structure, data, control hazards. Structure Not enough hardware or “resources” Assume that there only one memory unit and it stores instructions and data 1 2 3 4 5 add Access Mem for Fetch SW Access Mem for Fetch if ex Access memory for writing data (DM) I3 Access Mem for Fetch I4 Access Mem for Fetch I5 Access Mem for Fetch (IM) …. Access Mem for Fetch ….. bne if Id ex lw If Id Ex use ALU bne if Id Ex add (I18 12 +I6) Problem: two instructions (LW and I5) are trying to access memory One memory unit? Conflict split the memory into two units IM and DM Practically the access is done to the cache – 1 memory unit and two cache units (IC, DC) Assume that I want to work in multi-threading two threads Thread 1 Thread 2 Add $1, $2, $3 Add $4, $5, $6 Problem 2 ALU operations at the same time ➔ add one more ALU We may need to calculate the brunch address ($18 I12 + I6)need to execute an add instriction) Solution 1 ALU and 1 adder For structure hazards at design time duplicate resources. ALU and adder for PC PC +4 an adder fro branch 2 memory units Data hazards One embodiment Read before write I1, I2 I2 needs to read data before I1 was able to write it (WB) I1 Add $s0, $t0, $t1 I2 Sub $t2, $s0, $t3 Add If Id Ex (S0 is known) Mem WB $s0 is available in RF sub If Id Ex need $s0 Mem wb Solution 40 insert delays Forwarding Take the value out of EX in the add instruction and forward it to the input to ex in the sub solution (41) One of the inputs of the ALU can be the output of the ALU 10/07 Addi Addi $22, $23, 1025 $22 $23 + 1025 IF I4 IM[PC] ; // 001000 10111 10110 0000 0010 0000 0001 //??? I2 PC + 4 ID CLU IR[31-26] || IR[5-0] // Addi RR1 IR[25-21] // 23 (&23) RR2 IR[20-16] // jnk I8 * $23 // * === contents I10 jnk I6 I2 I12 SE[IR[15-0]] constant in instruction Such as addi // 0000 0000 0000 0000 0000 0010 0000 0001 I14 &$rt // 23 I16 &$rd // jnk IF and ID are done; identically done for each instruction Ex I26 I8 + I12 // I26 is ALU results I30 I14 AluSrc 1 // to get I12 as the second input to the ALU. RegDst