Design a pipeline processor for the given single cycle CPU/datapath
Microsoft Word - Document1 Design a pipeline processor for the given single cycle CPU/datapath. The ISA for this processor is given in the next page: iii. Design (sections: a, b, c and d) iv. Name of each member who works on each section. v. Conclusions vi. References vii. Appendix (should include any extra information related to the project) Computer Organization and Design: The Hardware/Software Interface In Praise of Computer Organization and Design: The Hardware/ Software Interface, Fifth Edition “Textbook selection is oft en a frustrating act of compromise—pedagogy, content coverage, quality of exposition, level of rigor, cost. Computer Organization and Design is the rare book that hits all the right notes across the board, without compromise. It is not only the premier computer organization textbook, it is a shining example of what all computer science textbooks could and should be.” —Michael Goldweber, Xavier University “I have been using Computer Organization and Design for years, from the very fi rst edition. Th e new Fift h Edition is yet another outstanding improvement on an already classic text. Th e evolution from desktop computing to mobile computing to Big Data brings new coverage of embedded processors such as the ARM, new material on how soft ware and hardware interact to increase performance, and cloud computing. All this without sacrifi cing the fundamentals.” —Ed Harcourt, St. Lawrence University “To Millennials: Computer Organization and Design is the computer architecture book you should keep on your (virtual) bookshelf. Th e book is both old and new, because it develops venerable principles—Moore's Law, abstraction, common case fast, redundancy, memory hierarchies, parallelism, and pipelining—but illustrates them with contemporary designs, e.g., ARM Cortex A8 and Intel Core i7.” —Mark D. Hill, University of Wisconsin-Madison “Th e new edition of Computer Organization and Design keeps pace with advances in emerging embedded and many-core (GPU) systems, where tablets and smartphones will are quickly becoming our new desktops. Th is text acknowledges these changes, but continues to provide a rich foundation of the fundamentals in computer organization and design which will be needed for the designers of hardware and soft ware that power this new class of devices and systems.” —Dave Kaeli, Northeastern University “Th e Fift h Edition of Computer Organization and Design provides more than an introduction to computer architecture. It prepares the reader for the changes necessary to meet the ever-increasing performance needs of mobile systems and big data processing at a time that diffi culties in semiconductor scaling are making all systems power constrained. In this new era for computing, hardware and soft ware must be co- designed and system-level architecture is as critical as component-level optimizations.” —Christos Kozyrakis, Stanford University “Patterson and Hennessy brilliantly address the issues in ever-changing computer hardware architectures, emphasizing on interactions among hardware and soft ware components at various abstraction levels. By interspersing I/O and parallelism concepts with a variety of mechanisms in hardware and soft ware throughout the book, the new edition achieves an excellent holistic presentation of computer architecture for the PostPC era. Th is book is an essential guide to hardware and soft ware professionals facing energy effi ciency and parallelization challenges in Tablet PC to cloud computing.” —Jae C. Oh, Syracuse University This page intentionally left blank Computer Organization and Design T H E H A R D W A R E / S O F T W A R E I N T E R F A C E F I F T H E D I T I O N David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, where he holds the Pardee Chair of Computer Science. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. Th is record led to Distinguished Service Awards from ACM and CRA. At Berkeley, Patterson led the design and implementation of RISC I, likely the fi rst VLSI reduced instruction set computer, and the foundation of the commercial SPARC architecture. He was a leader of the Redundant Arrays of Inexpensive Disks (RAID) project, which led to dependable storage systems from many companies. He was also involved in the Network of Workstations (NOW) project, which led to cluster technology used by Internet companies and later to cloud computing. Th ese projects earned three dissertation awards from ACM. His current research projects are Algorithm-Machine-People and Algorithms and Specializers for Provably Optimal Implementations with Resilience and Effi ciency. Th e AMP Lab is developing scalable machine learning algorithms, warehouse-scale-computer-friendly programming models, and crowd-sourcing tools to gain valuable insights quickly from big data in the cloud. Th e ASPIRE Lab uses deep hardware and soft ware co-tuning to achieve the highest possible performance and energy effi ciency for mobile and rack computing systems. John L. Hennessy is the tenth president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. In 1981, he started the MIPS project at Stanford with a handful of graduate students. Aft er completing the project in 1984, he took a leave from the university to cofound MIPS Computer Systems (now MIPS Technologies), which developed one of the fi rst commercial RISC microprocessors. As of 2006, over 2 billion MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy subsequently led the DASH (Director Architecture for Shared Memory) project, which prototyped the fi rst scalable cache coherent multiprocessor; many of the key ideas have been adopted in modern multiprocessors. In addition to his technical activities and university responsibilities, he has continued to work with numerous start-ups both as an early-stage advisor and an investor. Computer Organization and Design T H E H A R D W A R E / S O F T W A R E I N T E R F A C E David A. Patterson University of California, Berkeley John L. Hennessy Stanford University AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Morgan Kaufmann is an imprint of Elsevier With contributions by Perry Alexander Th e University of Kansas Peter J. Ashenden Ashenden Designs Pty Ltd Jason D. Bakos University of South Carolina Javier Bruguera Universidade de Santiago de Compostela Jichuan Chang Hewlett-Packard Matthew Farrens University of California, Davis David Kaeli Northeastern University Nicole Kaiyan University of Adelaide David Kirk NVIDIA James R. Larus School of Computer and Communications Science at EPFL Jacob Leverich Hewlett-Packard Kevin Lim Hewlett-Packard John Nickolls NVIDIA John Oliver Cal Poly, San Luis Obispo Milos Prvulovic Georgia Tech Partha Ranganathan Hewlett-Packard F I F T H E D I T I O N Library of Congress Cataloging-in-Publication Data Patterson, David A. Computer organization and design: the hardware/soft ware interface/David A. Patterson, John L. Hennessy. — 5th ed. p. cm. — (Th e Morgan Kaufmann series in computer architecture and design) Rev. ed. of: Computer organization and design/John L. Hennessy, David A. Patterson. 1998. Summary: “Presents the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O”— Provided by publisher. ISBN 978-0-12-407726-3 (pbk.) 1. Computer organization. 2. Computer engineering. 3. Computer interfaces. I. Hennessy, John L. II. Hennessy, John L. Computer organization and design. III. Title. British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library ISBN: 978-0-12-407726-3