ECE347 Resets and Interrupts Practice Work
ECE347_HW9_Resets_and_Interrupts ECE347 Resets and Interrupts Practice Work PI = 3 1. Write the code needed to set the normal reset vector to the location called START. 2. Write the code needed to enable the clock monitor reset, and set the COP timer to about 65 ms, assuming a 4MHz oscillator clock. 3. Write the code to initialize the vectors for the COP and clock monitor. 4. Write the instructions needed in the MAIN BACKGROUND LOOP that reset the COP timer. 5. Write the interrupt service routines for COP and clock monitor to behave as described in the following P-code: COP interrupt: ERROR_CODE = $32 COP_LOOP GOTO COP_LOOP Clock monitor interrupt: ERROR_CODE = $47 CM_LOOP GOTO CM_LOOP M_09_Lecture_01_Resets_Interrupts ECE347Module9Lecture1 ResetsandInterrupts 1 Module9Lecture1Objectives Inthislecture,youwilllearn: • Whataresetisandhowtoinitializetheresetvectors • HowtheCOPandclockmonitorsystemsoperate • Whataninterruptisandhowitworks • AlloftheHC12interruptsources • Howtoprogramforinterrupts • OperatingmodesoftheHC12 2 Whatisaninterrupt? Aspecialevent(externalorinternal) thatforcestheCPUtodivertfromthe mainprogramandperformsome servicerelatedtotheevent.Examples ofinterruptsourcesincludeexternal switchpress,internaltimertime-out, datareceivedfromtheserialport,etc. Thecodethatrunsduringaninterrupt iscalledaninterruptserviceroutine,or ISR. LOOPMAIN InterruptService Routine FunctionsofInterrupts - CoordinatingI/Oactivitiessuchasreceivingortransmittingdata - Providingawaytogracefullyexitfromerrorsandwarnusersofproblems - AlertingtheCPUtoperformroutinetaskssuchasbatterycheck InterruptMaskability - InterruptsthatcanbeignoredbytheCPUarecalledmaskableinterrupts. - Interruptsthatcan’tbeignoredbytheCPUarecallednonmaskableinterrupts. InterruptProgramming Thereareseveralthingsthattheprogrammermustdotoincorporateinterruptcode: Allocatestackspace Initializetheinterruptvector- seenextslide Initializethestackpointer Configuretheinterruptoperation EnableGLOBALinterruptflag(CLI) EnableLOCALinterruptflag(sourcedependent) Writetheinterruptserviceroutine nonmaskable maskable default priority level lowest highest Interruptpriority ThepriorityistheorderinwhichtheCPUwillserviceinterruptswhenseveralinterrupts occuratthesametime. ThepriorityontheHC12isfromtopdownonthelistofvectoraddresses.Resetshave highestpriority,followedbynonmaskableinterrupts,followedbymaskableinterrupts. Aninterrupt’sprioritymayberaisedtothetopofthemaskablelistbyprogrammngthe HPRIO registertocontainthatsource’slowbytevectoraddress.Forexample,tomake TIMERCHANNEL1thehighestmaskablepriority,onewoulduse: LDAA#$EC STAAHPRIO Resets Resetsaresimilartointerruptsinthattheflowofcodeexecutionischanged.Inareset, however,themaincodeisstopped,andthecodeBEGINSaprogramexecutionstarting atthelocationspecifiedinthevector. Therearetwonormalresets,poweroff/on,andtheresetpin.Bothoftheseusethesamevector, whichisatthetopofthelist:$FFFEand$FFFF.ThecodeMAINaddressshouldbeinitializedwithin thisvectorasfollows: ORG$FFFE FDBMAIN;makesureMAINcodeusesthislabel Thiscodeinitializesthenormalresetvector,soafterpoweruporresetswitchpress, thenormalcodewillrun. Resets Therearetwoabnormalresets,clockmonitorfail(CLKMON),andCOPtimeout. Clockmonitorfailmeansthateithertheoscillatorcrystalisbad,ortheMCUXTALpin inputisbad.Ineithercase,thecodewon’trunrightandtheusershouldbenotified ofaHARDWAREerror.Generally,wewritecodetorespondtoCLKMONfailbyissuing anerrorwarning,thenstayinginaninfinitetraploop.Aswiththenormalreset,wealso needtoinitializethevector.Here’sthevectorinitcode: ORG$FFFC FDBCM_FAIL;makesureclockmonitorcodeusesthislabel Andtheerrorhandlingcodemightlooklikethis: ORG$C500 CM_FAIL LDAA#1 STAAHW_FLAG;setHWbadindicatorforuser CM_TRAPNOP BRACM_TRAP Resets COPstandsforComputerOperatingProperlyandisanothernamefor“watchdogtimer.” Theideahereisatimerissetthatshouldnottimeoutfornormalcodeoperation.Ifitdoestime out,itmeansthereisaseriousSOFTWAREerror.Again,theusershouldbenotifiedofatheproblem inasimilarmannerasbefore,thatis,wewritecodetorespondtoCOPfailbyissuinganerrorwarning, thenstayinginaninfinitetraploop.Here’sthevectorinitcodeforCOPtimeout: ORG$FFFA FDBCOP_FAIL;makesureCOPcodeusesthislabel Andtheerrorhandlingcodemightlooklikethis: ORG$C600 COP_FAIL LDAA#1 STAASW_FLAG;setSWbadindicatorforuser COP_TRAPNOP BRACOP_TRAP Resets Unlikeanormalreset,COPandCLKMONmustbeenabledandconfigured.Thisisdoneusingthe COPCTLregisterandthevaluesinthetablebelow.TheCMEbit(b7=1)turnsonCLKMON.The setofbitsCR2,CR1,CR0setthetimeouttimefortheCOPtimer. Table 6.2 COP watchdog rates (RTBYP = 0) CR2 CR1 CR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Divide E by off 213 215 217 219 221 222 223 At E = 4.0 MHz timeout 0 to 2.048 ms At E = 8.0 MHz timeout 0 to 1.024 ms off 2.048 ms 8.192 ms 32.768 ms 131.072 ms 524.288 ms 1.048 s 2.097 s off 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 s COPTimerReset Onemorething... TheCOPtimerneedstobereseteachtimethroughthemaincodeloop.ThisisdoneusingtheCOPRST register.Withinthemainloop,thecodeforresettingtheCOPtimerlookslikethis: ...inmainloopLDAA#$55 STAACOPRST LDAA#$AA STAACOPRST Example1. Writeacodesegmentthatinitializesthenormalresetvector,clockmonitorvector,and theCOPvector.ThecodeshouldalsoenableCLKMONandCOP,andsettheCOPtime outtoabout8msforanoscillatorclockof8MHz.Themainloopofthecodeshould resettheCOPtimer,anderrortrapsshouldbewrittenforCLKMONandCOP. SolutiontobedoneinCodeWarrior. 14 Solution ;RegDefs COPCTLEQU$003C ARMCOPEQU$003F ;vectorinit ORG$FFFE FDBMAIN;Normalresetvectorinit ORG$FFFC FDBCM_FAIL;failedCLKMONvectorinit ORG$FFFA FDBCOP_FAIL;failedCOPvectorinit ;StackAllocation ORG$1000 STKTOPRMB10 STKBTMRMB1 continued... 15 ;Normalcode ORG$C000 MAINSEI;maskallints LDS#STKBTM;SPinit LDAA#$82;%10000010,CR2-1-0=010for8mstimeout,FreqE=4MHz STAACOPCTL CLI;unmaskints=enableGLOBALintflag NOP BG_LOOPNOP NOP LDAA#$55; STAAARMCOP; LDAA#$AA; STAAARMCOP;resetCOPtimer NOP NOP BRABG_LOOP continued... 16 ;resettraps ORG$C200 CM_FAILNOP BRACM_FAIL ORG$C300 COP_FAILNOP BRACOP_FAIL Notethatthesimulator/debuggerbydefaultturnsoffCOPandCLKMON.This makestotalsensebecauseanybreaksorstepswouldimmediatelyresultinatime out.Thus,itischallengingtodebugcodethatisrelatedtoCOPandCLKMON. InterruptProgramming- reminder Thereareseveralthingsthattheprogrammermustdotoincorporateinterruptcode: Allocatestackspace Initializetheinterruptvector Initializethestackpointer Configuretheinterruptoperation EnableGLOBALinterruptflag(CLI) EnableLOCALinterruptflag(sourcedependent) Writetheinterruptserviceroutine IRQN– externalinterruptpin TheIRQNorIRQ-not(the“not”meaningactivelow)isavailableontheHC12toallowaswitch presstocauseaninterrupt.Thisinterruptsourcehasanassociatedconfigurationregister calledINTCR,whichallowsforedge/leveldetect(bit7,edge=1),enable(bit6=1),anddelay (bit5=1)functionsasshownintheimagebelow.Theedge/levelselectionallowsforsetting thedesiredswitchoperation.Enableturnstheinterrupton– thisistheLOCALenable bit.DLYisusedtodelaytheinterruptfrombeingactiveforafewmomentsduringsystem startup. Example2. WriteaMAINcodesegmentthatinitializestheIRQNvector,andenablesIRQNwithedge triggering.AlsowriteanIRQNISRthatincrementsacountereachtimeitruns. ThesolutionshouldbedoneinCodeWarriorandobservedusingthedebuggeron realhardware.Inordertodothis,oneneedstoconnecttheIRQNpintoapulledup switch.Thisisdescribedindetailinthedemolabdocumentation. 20 Solution ;vectorsinit ORG$FFFE FDBMAIN;normalresetvector ORG$FFF2 FDBIRQN_ISR;IRQNvector ;stackallocation ORG$1000 STKTOPRMB10 STKBTMRMB1 IRQ_COUNTRMB1 ;registerdefs INTCREQU$001E continued... 21 ;maincode ; ORG$C000 MAINSEI LDS#STKBTM;SPinit LDAA#%11000000;IRQNedgetriggered,enabled STAAINTCR;storetoIRQcontrolregister CLRIRQ_COUNT;count=0atstartup CLI;clearintmask=enableglobalints NOP BG_LOOPNOP NOP;doimportantbackgroundstuffhere NOP BRABG_LOOP continued... 22 ;interruptserviceroutine ; ORG$C500 IRQN_ISRNOP NOP INCIRQ_COUNT;count=count+1 NOP NOP RTI;returntomain Notethatthesimulator/debuggerdoesnotworkforinterrupts.Youwillneed torunthiscodeinsomerealHC12hardwaretoobserveitsoperation. WhattheMCUdoesduringaninterrupt Thepreviousexampleillustratedallthethingstheprogrammermustdotomakeinterrupts work.TheCPUalsodoesquiteafewthings(automatically)whichareinterestingtonote. HerearethethingsthatoccurintheMCUafteraninterrupttriggerisdetected: 0.Finishthecurrentinstruction 1.Saveallregisters(exceptSP)onthestack 2.Identifycauseoftrigger 3.Getvectorcontents(ISRaddress)fromappropriatevector 4.ExecuteISRuntilRTIisexecuted 5.Restoreallregisters(exceptSP)fromthestack 6.ResumeMAINloopexecution Sinceinterruptscauseallregisterstobestacked,thismeansthestacksizeneedstobe biggerifyou’reusinginterrupts. RegisterStackingOrder Theregistersgetpushedontothestackintheordershownbelow. Symbol Data STKTOP CCR A B XHi XLo Y Hi Y Lo RTN Hi RTN Lo STKBTM -- OperatingModes TheHC12hasseveraldifferentoperatingmodes.Somemodesareforsavingbatterylife,othersare forbackgrounddebugmode,othersareforchangingthesizeofthedefaultdatabus.Thesemodes arecontrolledaccordingtothetablebelow,orbyincorporatingspecialinstructionsinthecode, suchasSTOPandWAIT. WhenaWAIT isexecuted:Allregistersarestacked.CPUclockisstopped.Peripheralclockscontinuerun. AninternalinterruptcanwakeuptheCPU.Thisis“doze”mode. WhenaSTOP isexecuted:Allregistersarestacked.Allclocksarestopped.Anexternalinterrupt(switch press)isneededtowakeuptheCPU.Thisis“deepsleep”mode. Table 6.5 68HC12 Mode Selection BKGD MODB MODA Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Special single chip Special expanded narrow Special peripheral Special expanded wide Normal single chip Normal expanded narrow Reserved (forced to peripheral) Normal expanded wide Port A general-purpose I/O ADDR[15:8]DATA[7:0] ADDR/DATA ADDR/DATA General-purpose I/O ADDR[15:8]DATA[7:0] -- ADDR/DATA Port B general-purpose I/O ADDR[7:0] ADDR/DATA ADDR/DATA General-purpose I/O ADDR[7:0] -- ADDR/DATA Module9Lecture1Summary Inthislecture,youhavelearned: • Whataresetisandhowtoinitializetheresetvectors • HowtheCOPandclockmonitorsystemsoperate • Whataninterruptisandhowitworks • AlloftheHC12interruptsources,particularlyIRQN • Howtoprogramforinterrupts • OperatingmodesoftheHC12andSTOP/WAIToperation 26