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EECE.2650 Logic Design Project 4Due Friday 4/30/21 Objective: The objective of this assignment is to design a Serial Arithmetic Processor. PART I. Design Design Specifications: Design a Serial Arithmetic Processing Unit (APU) that performs a set of operations on up to two 4-bit binary numbers based on a 3-bit operation code (OpCode). Be sure to use the archived project “alu_design” on Blackboard which contains a template for this project. Inputs: clk: clock input, 10ns period 50% duty-cycle Data[3..0]: 4-bits of Data (shared bus between both registered) RESET: Active low reset that sets the APU to an initial state, with all data set to zero. OpCode[2..0]: 3-bit Control input that represents a code for each operation. START: 1-bit Control input that starts the operation after the OpCode has been set. Outputs: A[3..0]: 4-bit result (Note: All operations overwrite R1 to store the result) ALU Function Set OpCode Function 000 A -> A 001 A+B+1 -> A (addition with carry) 010 A’ -> A (Complement) 011 B – A -> A (subtraction) 100 -A -> A (Mathematical Negative A) 101 B - A - 1 -> A (subtraction with borrow) 110 A + 1 -> A (increment A by 1) 111 A+B -> A (addition) Design: The design will consist of 3 modules: A Data Path, a State Generator, and a Control Circuit. The final circuit will connect these three modules to the inputs and outputs listed above. Each of the following sections should be its own bdf file. Data Path:2:1 Mux truth table S Y 1 A 0 B Data Path Hardware: Note: the included .qar file has a template data path for you to work with TWO universal shift/parallel load registers (74194) : R1,R2 ONE 1-bit Full adder (from Assignment 2) ONE D-Type FF (for the carry) One 4:1 Multiplexer for the carry (74153M in Quartus – see details in the Specialized Chips section) Two 2:1 Input Processor Multiplexers (21mux in Quartus– see details above) NOT Gates, GND (‘0’), VCC (‘1’) connections No other gates should be needed in this section. Data Path Inputs:Data Path Outputs: s1_R1, s0_R1 : controls for R1 RegisterA[3..0] : sum is stored in R1 s1_R2, s0_R2 : controls for R2 Register rst : asynchronous active-low reset clk : clock input Data[3..0] : Parallel Load Input Data (Note that this is shared between both registers) Sel_A, Sel_B, (select bits for each 2:1 MUX in the Input Processor) c0 (Initial carry for the serial adder) C1, C2 : Carry Mux Selector Bits (to choose holding the carry, the carry from the full adder, or the initial carry c0) Goals: 1. Fill in the Datapath module table in the project 4 template document. 2. Using the table, determine how to wire up the two 2:1 muxes that act as input selectors for the full adder. 3. Using the bdf template in the project, wire up the arithmetic processor. You may only use wires, NOT gates, GND (‘0’), and VCC (‘1’) 4. Add a screenshot to the project 4 template document. Optional: To test your Datapath you can manually set the control signals I have set up the one below to add A=5 and B=2: as you can see the result is 7 I suggest you test all 8 combinations before moving on. Here is one for 2-5 = -3 State Generator: The State Generator should be designed to cycle through each state of the operation. Since these are 4-bit numbers, the operation will use 6 clock cycles, Load R1, Load R2, and 4 shift operations. Consult the ASM chart later in this document for details on the states. State Generator Behavior: Hold in the initial state (T0) until START is set to 1 Move through the remaining 5 states and return to T0 when completed. The value of START does not matter while in states 1-5 Asynchronously return to the initial state (T0) when the system RESET is ‘0’ See the State Generator in Chapter 11 of the textbook as an example. State Generator Hardware: For the state generator you should use 6 States with 1-hot encoding. You can utilize the following chips: Unlimited AND, OR, NOT, XOR, XNOR Gates 6 DFF State Gen Inputs:State Gen Outputs: RESET : active-low reset T[0..5] : present state that sets the state generator to T0 START : Start Command clk : system clock Goals: 1. Based on the specifications above, draw a state diagram for the state generator in the project 4 template document. 2. Fill out the transition table for the state generator in the project 4 template document. 3. Use the state table, find the Next State Equations for T0-T5 (record them in the project 4 template document). 4. Build the state generator in Quartus using the supplied bdf file. 5. Add a screenshot to the project 4 template document. Recommended: Test your state generator, it should match the simulation below Control Circuit: The Control Circuit is a purely combinational circuit that works alongside the State Generator to take the user inputs and translate them into signals for the Data Path. Control Circuit Inputs:Control Circuit Outputs: OpCode[2..0]Sel_A, Sel_B, c0 T[0..5] C2, C1 STARTs1_R1, s0_R1 s1_R2, s0_R2 Control Circuit Hardware: Unlimited AND, OR, NOT, XOR, XNOR Gates Goals: 1. Fill in the OpCode Control Circuit truth table on the project 4 template document based on how you connected the Datapath. 2. Use the table to find equations for Sel_A, Sel_B and c0. 3. Fill in the State Generator Control Circuit truth table on the project 4 template document. 4. Use the table to find equations for s1_R1 s0_R1 s1_R2 s0_R2C2 C1 5. Build the control circuit in Quartus 6. Add a screenshot to the project 4 template document. Note: The shift registers operate based on the following table: The Serial adder has been setup to Shift Right when adding. MODE S1 S0 HOLD 0 0 SHIFT LEFT 1 0 SHIFT RIGHT 0 1 PARALLEL LOAD 1 1 ASM CHART: Note: Hold Everything means s1s0 = 00 for both registers and C2C1 = 11 Specialized Chips used in this design: 21MUX in the symbol Library. S Y 1 A 0 B 74153M 4:1 Mux with ACTIVE_LOW ENABLE (GN) B A Y 0 0 C0 0 1 C1 1 0 C2 1 1 C3 74194 Shift Register: MODE CLRN S1 S0 QA QB QC QD RESET 0 X X 0 0 0 0 HOLD 1 0 0 QA QB QC QD SHIFT LEFT 1 1 0 QB QC QD SLSI SHIFT RIGHT 1 0 1 SRSI QA QB QC PARALLEL LOAD 1 1 1 A B C D X = Don’t care All transistions except for the asynchronous reset occur on RISING CLOCK EDGE DFF is a D-type Flip flop that updates on the Rising Clock Edge: PRN = asynchronous ACTIVE-LOW PRESET CLRN = asynchronous ACTIVE-LOW CLEAR D Q 0 0 1 1 Final Design: Goals: 1. Take each Block Diagram File for the three circuit modules above and turn them into individual .bsf files 2. Connect the bsf files in a single bdf as below: There should be no additional gates in the block diagram. Part II: Test Test each OpCode by doing 8 simulations. Each simulation should last for 100ns. Set START = 1 from 20ns to 30ns. Clock = 10ns period, 50% duty cycle Use the template below for your simulations: For all simulations, A = 5, B = 2 which should yield the following results: OpCode Result 0 0 0 5 0 0 1 -8 0 1 0 -6 0 1 1 -3 1 0 0 -5 1 0 1 -4 1 1 0 6 1 1 1 7 Part III: Submission Use the separate document, Project 4 Template for your submission. Submit only that PDF. Name: EECE.2650 Logic Design Project 4 Design of Arithmetic Processing Unit Datapath Module: Data Path Table: Use this table to determine which signals go where for each instruction. You can then use this table to wire your datapath so that the muxes route the correct signals The add instruction is filled out for you as an example. OpCode[2:0] Instruction xi yi c0 0 0 0 A -> A 0 0 1 A+B+1 -> A 0 1 0 A’ -> A 0 1 1 B – A -> A 1 0 0 -A -> A 1 0 1 B - A -1 -> A 1 1 0 A + 1 -> A 1 1 1 A+B -> A Ai Bi 0 Completed Datapath: State Diagram for the State Generator: Transition Table for the State Generator: (The initial state of the machine is filled out as an example) Present State START Next State T0 0 T0 Using the table above, find the Next State Equations for T0-T5. Block Diagram for state generator: OpCode Control Circuit Truth Table: (The add instruction is filled out for you as an example) OpCode[2:0] Instruction Sel_A Sel_B c0 0 0 0 A -> A 0 0 1 A+B+1 -> A 0 1 0 A’ -> A 0 1 1 B – A -> A 1 0 0 -A -> A 1 0 1 B - A -1 -> A 1 1 0 A + 1 -> A 1 1 1 A+B -> A 1 1 0 State Generator Control Circuit Truth Table: (The initial state of the machine is filled out as an example) Present State START s1_R1 s0_R1 s1_R2 s0_R2 C2 C1 T0 0 0 0 0 0 1 1 Equations for each control signal: (You may choose to use a KMAP for each signal) Block Diagram for Control Circuit: Block Diagram for Completed Circuit: Testing of ALU: Paste images showing each OpCode being performed successfully below. Be sure to label each image with the Opcode being used and its instruction. You should have 8 screenshots Example: Simulation for OpCode 000, A->A:

EECE.2650 Logic Design Project 4Due Friday 4/30/21 Objective: The objective of this assignment is to design a Serial Arithmetic Processor. PART I. Design Design Specifications: Design a Serial Arithmetic Processing Unit (APU) that performs a set of operations on up to two 4-bit binary numbers based on a 3-bit operation code (OpCode). Be sure to use the archived project “alu_design” on Blackboard which contains a template for this project. Inputs: clk: clock input, 10ns period 50% duty-cycle Data[3..0]: 4-bits of Data (shared bus between both registered) RESET: Active low reset that sets the APU to an initial state, with all data set to zero. OpCode[2..0]: 3-bit Control input that represents a code for each operation. START: 1-bit Control input that starts the operation after the OpCode has been set. Outputs: A[3..0]: 4-bit result (Note: All operations overwrite R1 to store the result) ALU Function Set OpCode Function 000 A -> A 001 A+B+1 -> A (addition with carry) 010 A’ -> A (Complement) 011 B – A -> A (subtraction) 100 -A -> A (Mathematical Negative A) 101 B - A - 1 -> A (subtraction with borrow) 110 A + 1 -> A (increment A by 1) 111 A+B -> A (addition) Design: The design will consist of 3 modules: A Data Path, a State Generator, and a Control Circuit. The final circuit will connect these three modules to the inputs and outputs listed above. Each of the following sections should be its own bdf file. Data Path:2:1 Mux truth table S Y 1 A 0 B Data Path Hardware: Note: the included .qar file has a template data path for you to work with TWO universal shift/parallel load registers (74194) : R1,R2 ONE 1-bit Full adder (from Assignment 2) ONE D-Type FF (for the carry) One 4:1 Multiplexer for the carry (74153M in Quartus – see details in the Specialized Chips section) Two 2:1 Input Processor Multiplexers (21mux in Quartus– see details above) NOT Gates, GND (‘0’), VCC (‘1’) connections No other gates should be needed in this section. Data Path Inputs:Data Path Outputs: s1_R1, s0_R1 : controls for R1 RegisterA[3..0] : sum is stored in R1 s1_R2, s0_R2 : controls for R2 Register rst : asynchronous active-low reset clk : clock input Data[3..0] : Parallel Load Input Data (Note that this is shared between both registers) Sel_A, Sel_B, (select bits for each 2:1 MUX in the Input Processor) c0 (Initial carry for the serial adder) C1, C2 : Carry Mux Selector Bits (to choose holding the carry, the carry from the full adder, or the initial carry c0) Goals: 1. Fill in the Datapath module table in the project 4 template document. 2. Using the table, determine how to wire up the two 2:1 muxes that act as input selectors for the full adder. 3. Using the bdf template in the project, wire up the arithmetic processor. You may only use wires, NOT gates, GND (‘0’), and VCC (‘1’) 4. Add a screenshot to the project 4 template document. Optional: To test your Datapath you can manually set the control signals I have set up the one below to add A=5 and B=2: as you can see the result is 7 I suggest you test all 8 combinations before moving on. Here is one for 2-5 = -3 State Generator: The State Generator should be designed to cycle through each state of the operation. Since these are 4-bit numbers, the operation will use 6 clock cycles, Load R1, Load R2, and 4 shift operations. Consult the ASM chart later in this document for details on the states. State Generator Behavior: Hold in the initial state (T0) until START is set to 1 Move through the remaining 5 states and return to T0 when completed. The value of START does not matter while in states 1-5 Asynchronously return to the initial state (T0) when the system RESET is ‘0’ See the State Generator in Chapter 11 of the textbook as an example. State Generator Hardware: For the state generator you should use 6 States with 1-hot encoding. You can utilize the following chips: Unlimited AND, OR, NOT, XOR, XNOR Gates 6 DFF State Gen Inputs:State Gen Outputs: RESET : active-low reset T[0..5] : present state that sets the state generator to T0 START : Start Command clk : system clock Goals: 1. Based on the specifications above, draw a state diagram for the state generator in the project 4 template document. 2. Fill out the transition table for the state generator in the project 4 template document. 3. Use the state table, find the Next State Equations for T0-T5 (record them in the project 4 template document). 4. Build the state generator in Quartus using the supplied bdf file. 5. Add a screenshot to the project 4 template document. Recommended: Test your state generator, it should match the simulation below Control Circuit: The Control Circuit is a purely combinational circuit that works alongside the State Generator to take the user inputs and translate them into signals for the Data Path. Control Circuit Inputs:Control Circuit Outputs: OpCode[2..0]Sel_A, Sel_B, c0 T[0..5] C2, C1 STARTs1_R1, s0_R1 s1_R2, s0_R2 Control Circuit Hardware: Unlimited AND, OR, NOT, XOR, XNOR Gates Goals: 1. Fill in the OpCode Control Circuit truth table on the project 4 template document based on how you connected the Datapath. 2. Use the table to find equations for Sel_A, Sel_B and c0. 3. Fill in the State Generator Control Circuit truth table on the project 4 template document. 4. Use the table to find equations for s1_R1 s0_R1 s1_R2 s0_R2C2 C1 5. Build the control circuit in Quartus 6. Add a screenshot to the project 4 template document. Note: The shift registers operate based on the following table: The Serial adder has been setup to Shift Right when adding. MODE S1 S0 HOLD 0 0 SHIFT LEFT 1 0 SHIFT RIGHT 0 1 PARALLEL LOAD 1 1 ASM CHART: Note: Hold Everything means s1s0 = 00 for both registers and C2C1 = 11 Specialized Chips used in this design: 21MUX in the symbol Library. S Y 1 A 0 B 74153M 4:1 Mux with ACTIVE_LOW ENABLE (GN) B A Y 0 0 C0 0 1 C1 1 0 C2 1 1 C3 74194 Shift Register: MODE CLRN S1 S0 QA QB QC QD RESET 0 X X 0 0 0 0 HOLD 1 0 0 QA QB QC QD SHIFT LEFT 1 1 0 QB QC QD SLSI SHIFT RIGHT 1 0 1 SRSI QA QB QC PARALLEL LOAD 1 1 1 A B C D X = Don’t care All transistions except for the asynchronous reset occur on RISING CLOCK EDGE DFF is a D-type Flip flop that updates on the Rising Clock Edge: PRN = asynchronous ACTIVE-LOW PRESET CLRN = asynchronous ACTIVE-LOW CLEAR D Q 0 0 1 1 Final Design: Goals: 1. Take each Block Diagram File for the three circuit modules above and turn them into individual .bsf files 2. Connect the bsf files in a single bdf as below: There should be no additional gates in the block diagram. Part II: Test Test each OpCode by doing 8 simulations. Each simulation should last for 100ns. Set START = 1 from 20ns to 30ns. Clock = 10ns period, 50% duty cycle Use the template below for your simulations: For all simulations, A = 5, B = 2 which should yield the following results: OpCode Result 0 0 0 5 0 0 1 -8 0 1 0 -6 0 1 1 -3 1 0 0 -5 1 0 1 -4 1 1 0 6 1 1 1 7 Part III: Submission Use the separate document, Project 4 Template for your submission. Submit only that PDF. Name: EECE.2650 Logic Design Project 4 Design of Arithmetic Processing Unit Datapath Module: Data Path Table: Use this table to determine which signals go where for each instruction. You can then use this table to wire your datapath so that the muxes route the correct signals The add instruction is filled out for you as an example. OpCode[2:0] Instruction xi yi c0 0 0 0 A -> A 0 0 1 A+B+1 -> A 0 1 0 A’ -> A 0 1 1 B – A -> A 1 0 0 -A -> A 1 0 1 B - A -1 -> A 1 1 0 A + 1 -> A 1 1 1 A+B -> A Ai Bi 0 Completed Datapath: State Diagram for the State Generator: Transition Table for the State Generator: (The initial state of the machine is filled out as an example) Present State START Next State T0 0 T0 Using the table above, find the Next State Equations for T0-T5. Block Diagram for state generator: OpCode Control Circuit Truth Table: (The add instruction is filled out for you as an example) OpCode[2:0] Instruction Sel_A Sel_B c0 0 0 0 A -> A 0 0 1 A+B+1 -> A 0 1 0 A’ -> A 0 1 1 B – A -> A 1 0 0 -A -> A 1 0 1 B - A -1 -> A 1 1 0 A + 1 -> A 1 1 1 A+B -> A 1 1 0 State Generator Control Circuit Truth Table: (The initial state of the machine is filled out as an example) Present State START s1_R1 s0_R1 s1_R2 s0_R2 C2 C1 T0 0 0 0 0 0 1 1 Equations for each control signal: (You may choose to use a KMAP for each signal) Block Diagram for Control Circuit: Block Diagram for Completed Circuit: Testing of ALU: Paste images showing each OpCode being performed successfully below. Be sure to label each image with the Opcode being used and its instruction. You should have 8 screenshots Example: Simulation for OpCode 000, A->A:

Apr 29, 2021

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