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fa22_prep.dvi COSC 530: Midterm 1 Study Guide Your exam will cover topics from the lecture, textbook, and homeworks. You should be prepared to answer questions on the following concepts from each chapter. I encourage you to work through the suggested problems from your text for extra practice. I will post solutions to these practice problems on the course website prior to the exam. • Chapter 1: Introduction 1. Understand and be able to discuss trends in computing technology and performance over the last several decades. 2. Describe Moore’s Law and Dennard Scaling. How do these trends affect computing processor design and performance? 3. Compare the different classes of computers we discussed in class. How do market forces affect the design of computers in each class? 4. Be able to describe and classify instances of different classes of parallelism in applica- tions and hardware. 5. Understand Flynn’s taxonomy. Be able to classify different designs using the hierarchy. 6. What are the three main aspects of computer design discussed in class? 7. What are the main problems related to power consumption in modern computer design? What are some techniques computer designers have used to improve energy efficiency? 8. Be able to describe and give examples static and dynamic power consumption. 9. What is the learning curve in component manufacturing? 10. Be able to define the performance metrics response time and throughput. 11. What are the advantages and disadvantages of using the following types of programs to evaluate performance: kernels, toy benchmarks, synthetic benchmarks, and real applications? 12. What is meant by the principle of locality? Be able to define and distinguish examples of temporal and spatial locality. 13. Be able to describe and apply Amdahl’s Law. 14. Understand the relationship between clock cycle time, instruction count, and cycles per instruction, and how these factors contribute to CPU time. 15. For extra practice, work through the following problems (pp. 70 – 75): – 1.5 (a, b, and c) – 1.8 (a and b) – 1.13 (a and b) – 1.14 (a, b, and c) – 1.15 (a, b, c, d, and e). • Appendix B: Memory Hierarchy Review 1. Be able to describe the basic design, goals, and tradeoffs of the memory hierarchy. Why is the memory hierarchy an effective design strategy? 2. Be able to use and apply performance equations (CPU time, etc.) that take into account memory stall cycles. 1 3. What are the advantages and challenges of measuring memory performance in software as compared to hardware / architectural approaches? 4. Understand and be able to describe the distinction between direct-mapped, set asso- ciative, and fully associative caches. 5. Given a reference to a memory address and a cache configuration, be able to partition the address into block offset, block address, index, and tag bits. 6. Describe characteristics of, as well as advantages and disadvantages, of different policies for block replacement within a cache set. 7. Understand the implications and operation of different policies for handling writes in caches (i.e., write through vs. write back as well as write allocate vs. no write allocate on write misses). 8. Understand how the simple optimizations we studied in this appendix can affect mem- ory performance, and in particular, hit time, miss rate, and miss penalty. 9. What are the characteristics, limitations, advantages, and disadvantages of the follow- ing design decisions in processor caches: using separate caches for instructions and data, using larger block sizes, using higher associativity (with different size caches), multi- level caching, prioritizing reads over writes, and virtually indexed, physically tagged caches. 10. What is the distinction between compulsory, capacity, and conflict cache misses? 11. Know the difference between local and global hit rates. 12. Understand the difference between inclusion and exclusion policies for multilevel cache design. 13. What are some of the problems with purely virtual caches? 14. Understand the basic design and purpose of virtual memory in modern computing platforms. 15. Know the difference between virtual memory pages and segments. Be able to explain advantages and disadvantages of each approach. 16. Know the difference between internal and external fragmentation. 17. What is the purpose of address translation for virtual memory systems? 18. Understand the design and organization of standard page tables. What is the benefit of an inverted page table. 19. What is contained in a typical page table entry? 20. Understand the basics of virtual memory management (where virtual pages can be mapped in physical memory, how virtual to physical page translations are stored and maintained, policies for writes and write misses). 21. What is a translation lookaside buffer (TLB)? Understand how entries are stored and accessed in the TLB. 22. What are the advantages and disadvantages of a larger page size? 23. How does virtual memory support multiprogramming and isolation among processes running on the same platform? 24. Be able to describe the process of accessing memory, from the generation of a virtual address in the processor, how this address is translated to a physical address, and how the physical address is used to access caches and main memory. 25. For extra practice, work through the following problems (pp. B-60 – B-66): 2 – B.1 (a and b) – B.2 (a and b) – B.5 (a, b, c, and d) – B.8 (a, b, c, and d) – B.10 (a, b, and c) – B.13 – B.14 (a, b, c, and d). • Chapter 2: Memory Hierarchy Design 1. Understand the performance gap between processor and memory technology. How does the trend towards multi-core processing affect this performance gap? 2. Define latency and bandwidth as performance metrics for memory devices. 3. What are the main characteristics and tradeoffs between static RAM (SRAM) and dynamic RAM (DRAM) technologies? 4. Understand and be able to describe the DRAM subsystem organization using the terms we discussed in class (channels, DIMMs, ranks, banks, rows and columns). 5. Be able to describe the process of how data is accessed at the DRAM device level. What are the purposes of the precharge (PRE), activate (RAS), and read/write commands (CAS) in a modern DRAM system? 6. What is the difference between the open row vs. closed row policies for DRAM access? 7. Be able to compute DRAM access latency and performance given certain timing pa- rameters, row buffer management policies, and row hit rates. 8. Understand the factors that contribute to static and dynamic in modern RAM tech- nologies. What is the purpose of self refresh mode in DRAM? 9. Understand the advantages and disadvantages of the emerging memory technologies we discussed in class. Where do each of these technologies fit within the modern memory hierarchy? 10. Know the different types of errors that occur in memory devices and how they are typically handled. 11. Be able to describe the characteristics, limitations, advantages, and disadvantages of the following memory hierarchy optimizations we discussed in class: small and simple first- level caches, way prediction, pipelined caches, multibanked caches, nonblocking caches, critical word first and early restart, merging write buffer, compiler optimizations (code postitioning, array merging, loop interchange, and blocking), hardware prefetching, compiler controlled prefetching, and using high bandwidth memory (HBM) as a large, hardware-managed cache. 12. Understand the difference between the Loh-Hill and alloy cache stratgies for managing HBM as a cache. 13. Understand the mechanisms by which virtual memory isolates data for different tasks on the same platform. 14. What is the main purpose of a virtual machine monitor (VMM)? 15. How does a VMM virtualize memory for multiple guest operating systems running on the same set of hardware? What is the purpose of the shadow page table? 3 16. What are some examples of architectural extensions that have been used to enable more efficient virtualization of hardware resources? 17. For extra practice, work through the following problems (pp. 149, 154 – 161): – 2.1 (a, b, and c) – 2.8, 2.9, 2.10, 2.11, 2.12, 2.13 – 2.18 (a and b) – 2.20 (a and b) – 2.22 (a, b, and c) – 2.25 (a, b, and c) – 2.37 – 2.41 (a, b, c, d, and e) 4 Chapter 1 Chapter 1 Chapter 1 Chapter 2 Chapter 2 2.37 2.41 Chapter 1 Appendix B Appendix B Appendix B Appendix B