For the CMOS gate shown in Figure 9.75, perform an analysis of constant voltage scaling. (Assume that the oxide thickness and all gate dimensions are scaled by 1/s). 1 ≤ s ≤ 10.
1. Determine and plot the propagation delay vs. s, assuming 20 on-chip loads.
2. Determine and plot the dissipation vs. s, assuming 20 on-chip loads and ƒ = 0.05/tP.
Figure 9.75
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