EE210 Spring 2020 1 Introduction to Logic Design Traffic Light Controller Class Project EE210 Spring 2020 2 Traffic Light Controller For your remining lab experiments, you will design a traffic light...

Full project report + final output file (simulated circuit)


EE210 Spring 2020 1 Introduction to Logic Design Traffic Light Controller Class Project EE210 Spring 2020 2 Traffic Light Controller For your remining lab experiments, you will design a traffic light control logic on paper using combinational and sequential logic circuits. You will start with a block diagram (a simple diagram will be provided) and identify system components according to the system requirements. After that you develop a state diagram that defines the sequence of standard traffic light operation for a intersection; i.e. for main street and for a side street. General System Requirements: A digital controller is required to control a traffic light at the intersection of a busy main street and an occasionally used side street. The main street is to have a green light for a minimum of 10 seconds, 4 second caution light (yellow) between changes from green to red on both the main street and on the side street (i.e. yellow or amber), and 10 seconds for red light. The side streetlight sequence will be same as main street, however, to avoid accidents, both red light needs to be simultaneously on at least 2-3 seconds, every time it changes to green. EE210 Spring 2020 3 Traffic Light Block Diagram Timing Circuits Combinational Logic Clock Feedback-Trigger Main Side ON/OFF EE210 Spring 2020 4 Traffic Light Timing Diagram EE210 Spring 2020 5 Traffic Light Controller - Timing CLK QA QB QC QD REDM GRNM AMBM REDS GRNS AMBS 1 REDM = Red on the Main road REDS = Red on the Side road 5 10 15 20 24 EE210 Spring 2020 6 Traffic Light Controller - Timing REDM = Red on the Main road REDS = Red on the Side road CLK QA QB QC QD REDM GRNM AMBM REDS GRNS AMBS 1 5 10 15 20 25 EE210 Spring 2020 7 Project development guidelines 1. From the project requirements, you can develop a detailed block diagram. 2. Identify main tasks and sub-tasks: 2 roads, 6 LEDs, synchronization clock, etc., 3. Draw a comprehensive state (timing) diagram that shows the sequence of states in a system and the conditions for each state and transitions from one state to the next and make it synchronous with a “system” clock. 4. Design a system clock cycle that can be multiplied to obtain the required time frame for each light sequence. 5. Since it is a sequential logic problem, it is recommended to use a 4-bit (or perhaps more) counter build upon your choice of FFs to obtain the required time frame for each light sequence. EE210 Spring 2020 8 Project development guidelines (cont.) 6. Carefully write Boolean equation (evaluate) for each light condition for each clock cycle. 7. Simplify your equation with Karnaugh maps for each light condition and sequence. 8. If necessary, add “one-shots” to extend the on-time of the LEDs or shorten the timing of each LED. 9. Try to use fewer gates, and if possible, one type of gates, i.e., NOR, NAND or XORs. In other words, if you have an AND gate and NAND gate in your circuit, use NANDs to make ANDs. 10.Finally, use Autodesk Eagle electronics design software to draw your final circuit for simulation.