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Homework 3 ECE 485/585 Fall 2019 Homework 3 1. [25] Draw the design of a 64MB memory system (organized as 32M x 16 bit words) using 64 Mb SRAM chips (organized as 8M x 8). Clearly label all address, data, and chip select lines including their bit width. You can omit OE and WE signals. Assume data pins are bidirectional. 2. [25] Consider two SRAMs. One is 256K x 4 and has a tRC of 8 ns. The other is 64K x 16 and has a tRC of 10ns. a. [5] What are the effective bandwidths of the two devices? b. [5] Now, consider that the devices are to be used to provide data to a 32-bit bus. What is the data rate that can be sustained on the bus if it is driven by 8 of the 256Kx4 chips in parallel? c. [5] What is the corresponding bus data rate if two of the 64Kx16 SRAMs are used in parallel? d. [5] Ignoring control, power, and ground pins, discuss the trade-offs in pin count between a 1Mb SRAM organized as a x1 device or as a x16 device. Assume data pins are bidirectional. e. [5] Assume you have an embedded system that requires a new byte of memory data every 6ns. How might you use the 64K x 16 SRAM chip to achieve this? 3. [20] A particular 4Gb DDR4-1600 chip organized as 512M x 8 uses 12-12-12 timing. a. [10] Assuming the device is in the pre-charged state, how long (in nanoseconds) will it take to complete the read of a byte of data? Show your work. b. [10] Assuming the device is in the pre-charged state, how long (in nanoseconds) will it take to complete the read of a burst of data? Show your work. 4. [40] Consider the DDR3 chip depicted below. a. [10] What is the capacity of the chip? b. [10] How is it organized? c. [10] What is the page size? d. [10] Why are the column address bits 0, 1, 2 treated specially and what is their role with the READ FIFO and data mux? 5. [20] The cells in a DRAM must be periodically refreshed or data will be lost due to leakage. DDR3 specifications require refresh of each cell every 64ms at 85°C. This refresh period is reduced to 32ms at 95°C. Depending upon their capacity, DDR3 devices internally refresh one or more rows in all banks simultaneously using “all-banks-concurrent row refresh” so as to maintain a constant 8K refresh operations over the refresh period. a) [5] Consider the DDR3 DRAM chip depicted in problem 4 above. How many rows will be refreshed in each bank for each refresh command? b) [5] How often on average will a refresh command need to be issued for this device operating at 95°C to ensure all rows are refreshed during the refresh period? c) [5] The time required to complete a refresh command is tRFC. A 1Gb DDR3 DRAM might have a tRFC of 118ns while an 8Gb device might have a tRFC of 375ns. What accounts for this difference? d) [5] What percentage of time will the 8Gb device above spend doing refresh operations (and therefore be unavailable for processor memory requests)? Assume 95°C operating temperature. Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram Bank 5 Bank 6 Bank 7 Bank 4 Bank 7 Bank 4 Bank 5 Bank 6 15 Row- address MUX Control logic Column- address counter/ latch Mode registers 11 Co m m an d de co de A[14:0] BA[2:0] 15 Address register 18 256 (x32) 8,192 I/O gating DM mask logic Column decoder Bank 0 memory array (32,768 x 256 x 32) Bank 0 row- address latch and decoder 32,768 Sense amplifiers Bank control logic 18 Bank 1 Bank 2 Bank 3 15 8 3 3 Refresh counter 4 32 32 32 DQS, DQS# Columns 0, 1, and 2 Columns 0, 1, and 2 ZQCL, ZQCS To pullup/pulldown networks READ drivers DQ[3:0] READ FIFO and data MUX Data 4 3 Bank 1 Bank 2 Bank 3 DM DM CK,CK# DQS, DQS# ODT control ZQ CAL WE# ZQ RZQ CK, CK# RAS# CAS# CS# ODT CKE RESET# CK,CK# DLL DQ[3:0] (1 . . . 4) (1, 2) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) BC4 BC4 (burst chop) BC4 Column 2 (select upper or lower nibble for BC4) Data interface WRITE drivers and input logic A12VSSQ OTF OTF 2Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. R 10/14 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.© 2006 Micron Technology, Inc. All rights reserved. 6. [55] You are to design an 8 GB memory subsystem for a desktop PC system employing DDR4 SDRAM chips on a standard DIMM with ECC and 72 data lines (for data and ECC). The SDRAM chips use a 1KB page size, 8 banks. The DIMMs employed are 4GB PC4-25600 with timing (16-18-18-36) Assume a cache line fill results in 64 bytes being read from the DIMM. a) [5] How many SDRAMs are on the DIMM if 512M x 8 SDRAMs are used? b) [5] How many ranks would there be per DIMM? c) [5] How many ranks are there in the memory system? d) [5] What would be the impact of using 256M x 16 SDRAMs on the memory organization? Are there any disadvantages? e) [5] What is the maximum bandwidth of one DIMM? f) [5] Assuming a single memory channel, what is the total maximum bandwidth achievable with all the DIMMs? g) [5] How much time (in ns) is required from the presentation of the activate command until the end of the cycle during which the last bytes of data are transferred? Assume the bank is precharged. h) [5] Assuming we could always arrange it so that the bytes we want from memory are among the first 8 bytes of the burst, how much faster on average can we expect to get the data? Assume that the memory controller implements a closed-page policy, pre-charging after each access to a bank. Give your answer as a percentage improvement over not using this technique. i) [5] What is the ratio of the amount of time it will take to complete a read from a location requiring a bank activate command (page empty) versus a read from a location in an already open page (page hit)? j) [5] Assume a scenario in which the memory controller implements an open page policy. If a long sequence of memory references results in all page misses, what bandwidth can we expect? k) [5] How does the result in (j) above compare with the maximum theoretical maximum bandwidth of the PC4-25600 DIMM?