https://eclass.yorku.ca/pluginfile.php/4000486/mod_resource/content/2/LabK_EECS2021_VerilogLab4_F2022_v1_student_VERSIONEECS2021–LabK:BuildanotherCPU2022 StudentVERSIONEECS 2021 –...

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HI, ITS LAB K THAT I WANT TO GET THE ANSWER, BUT I ATTACHED LAB J MAYBE YOU WILL NEED INFORMATION FROM IT


https://eclass.yorku.ca/pluginfile.php/4000486/mod_resource/content/2/LabK_EECS2021_VerilogLab4_F2022_v1_student_VERSION EECS2021–LabK:BuildanotherCPU2022 StudentVERSION EECS 2021 – Lab K: CPUs, Take 2 (Verilog Lab #4) Dr. James Andrew Smith, PEng. (a modification of original lab by Dr. Hamzeh Roumani) Summary: You modelled an 8-bit or 32-bit CPU in the previous lab. Now, get more practice, extending your knowledge to 4-bits or 16-bits. Pre-Lab: You will have done all or most of Lab J. If you did not complete Lab J, move on and complete this lab, but rather than an 8- or 32-bit machine, you’re now looking at 4- bit or 32-bit. Intro to Verilog video on YouTube (https://youtu.be/3ZJNV9F3AB4) Simulink as a Circuit Simulator (https://youtu.be/NSbPNoVWMfU) An example logic circuit (in schematic form). An example logic circuit (in Verilog form) Due date for Lab Report. No report Lab Demo and Demo Grading: The lab is worth one mark. Demo 1: [0.5 marks] Full & correct demo of the module? 0.3 marks. Partially successful demo? 0.2 marks. 0 otherwise • LastnameV-Z:demoPart2fromLabJ(combinemux’sintoabus),buteither4-bitor16-bit. • LastnameA-G:demoPart3fromLabJ(arraybasedmux),buteither4-bitor16-bit. • LastnameH-M:demoPart4fromlabJ(4to1mux),buteither4-bitor16-bit. • Lastname:N-UdemoPart5fromLabJ(fulladder),buteither4-bitor16-bit. Demo 2: [0.5 marks] • DemotheentireCPU(either4-bitsor16-bits),asyoudidinLabJ. o Partialdemo?0.2marks o Nodemo?0. No demo? No mark in that category. Partial demo (doesn’t compile, at least one error in test): 50% for that category. EECS2021–LabK:BuildanotherCPU2022 StudentVERSION General Remote Lab Instructions While EECS 2021 students would normally use the Verilog tools in PRISM Centre of the Lassonde Building, Room 1004 and Room 1006, you can also access them via the EECS Remote Lab web interface system, a traditional SSH connection from Windows PowerShell or macOS Terminal, or on the web via EDA Playground. When editing your Verilog files (*.v) you can either edit a. WithinEDAPlayground b. On an editor in the SSH session (like vim, nano or emacs), either within remotelab.eecs.yorku.ca,orwithinansshsessionfromWindowsPowerShell, macOSTerminal,etc. c. Using an editor on your own personal computer that supports SFTP or equivalent(e.g.BBEdit,Textwrangler,EditPlus,etc.) Also, consider using Matlab/Simulink to simulate the any unfamiliar components or circuits before implementing the Verilog solution. The reason? A graphical tool like Simulink will help you lay out your parts and help you see how the system is supposed to work before writing up the text-based script. If something goes wrong you can look at Simulink to help debug and understand. Figure1UsinggraphicaltoolslikeSimulinkorMapleSimtoquicklyexamineyourcircuitaheadoftimeishelpful. EECS2021–LabK:BuildanotherCPU2022 StudentVERSION The Lab This is continuation of the first Verilog lab. You can model the circuits in this lab using a number of different Verilog solutions, including 1. Theinternal(toYorkU)SSHorGUIinterfaceforremotelab.eecs.yorku.ca 2. Theexternal(toYorkU)commercialsystem,EDAPlayground (edaplayground.com) The methods for implementation are slightly different due to the nature of the interfaces, but they can produce the same results. Part 1: Get to the mid-point in either a 4-bit or 16-bit system You are asked to do two demonstrations in this lab. Both are similar to Lab J. First, you are to demonstrate a component in the construction of either a 4-bit or 16-bit computer. Either • demoPart2fromLabJ(combinemux’sintoabus),either4-bitor16-bit. • demoPart3fromLabJ(arraybasedmux),either4-bitor16-bit. • demoPart4fromlabJ(4to1mux),either4-bitor16-bit. • demoPart5fromLabJ(fulladder),either4-bitor16-bit. Where the selection and marks associated with the demo are on the first page of this document. Example 4-bit project in EDA Playground Example 16-bit project in EDA Playground EECS2021–LabK:BuildanotherCPU2022 StudentVERSION Part 2: The CPU (4-bit or 16-bit) Having followed all the steps from Lab J, now combine the components to form either a 4-bit or 16-bit CPU. This is similar to the last step in Lab J, in which you were to have finished up with an 8-bit or 32-bit machine. Demo to the TA that you can successfully test the CPU (either 4-bit or 16-bit) using opcodes 6 or 7. https://eclass.yorku.ca/pluginfile.php/4000468/mod_resource/content/2/LabJ_EECS2021_VerilogLab2_F2022_v1_Student_VERSION EECS2021–LabJ:BuildaCPU2022 StudentVERSION EECS 2021 – Lab J: CPUs: From Busses to ALUs (Verilog Lab #3) Dr. James Andrew Smith, PEng. (a modification of original lab by Dr. Hamzeh Roumani) Summary: Let’s model circuits (like a mux) that have groups of multiple signal wires (e.g. a bus). This is the next stage in developing CPU-relevant components using Verilog. Pre-Lab: You are to prepare for the lab by reading over this document and by conducting Lab I. You may wish to peruse online sources of Verilog tutorials, as well. Intro to Verilog video on YouTube (https://youtu.be/3ZJNV9F3AB4) Simulink as a Circuit Simulator (https://youtu.be/NSbPNoVWMfU) An example logic circuit (in schematic form). An example logic circuit (in Verilog form) EECS2021–LabJ:BuildaCPU2022 StudentVERSION Marking Guide Lab Report [ 1 mark ] Single page report (PDF) submitted to eClass. Name of the course and your name and student ID at the top. Draw • the“4to1”Muxand[0.5marks] • “fulladder”schematics[0.5marks] as described in this lab, by hand (either on paper or using a drawing program like OneNote, but not a CAD program like Proteus) labelling all the wires, including inputs, outputs and wires in between components in a way that makes it clear that it could be implemented in Verilog. It is due on the Sunday after your lab. If the drawing has any errors in it, is difficult to read, or is mislabelled, then it is 0.25 marks for that drawing. 0 if no drawing submitted. Lab Demo [ 1 mark ] The lab is worth one mark with two demonstrations. Demo 1: [0.8 marks] • LastnameA-G:demoPart2(combinemux’sintoabus),either8-bitor32-bit.(0.7marks) • LastnameH-M:demoPart3(arraybasedmux),either8-bitor32-bit.(0.7marks) • LastnameN-U:demoPart4(4to1mux),either8-bitor32-bit.(0.7marks) • LastnameV-Z:demoPart5(fulladder),either8-bitor32-bit.(0.7marks) Full demo of the component needed for 0.7 marks. Partial demo (doesn’t compile, at least one error in test, etc.): 0.35 marks. The TA will ask you to explain the component that you are demonstrating. The TA will evaluate you on the proficiency of the answer: • Failingtomeetexpectations:Noanswerornounderstandingofthecomponent 0 /0.1 • Marginallymeetexpectations:Studentshowssomeunderstanding 0.05 /0.1 • Meetexpectations: Studentunderstandsthecomponent 0.1 /0.1 Demo 2: [0.2 marks] For the final 0.2 marks, demonstrate the entire CPU, either 8-bit or 32-bit. EECS2021–LabJ:BuildaCPU2022 StudentVERSION General Remote Lab Instructions While EECS 2021 students would normally use the Verilog tools in PRISM Centre of the Lassonde Building, Room 1004 and Room 1006, you can also access them via the EECS Remote Lab web interface system, a traditional SSH connection from Windows PowerShell or macOS Terminal, or on the web via EDA Playground. When editing your Verilog files (*.v) you can either edit a. WithinEDAPlayground b. On an editor in the SSH session (like vim, nano or emacs), either within remotelab.eecs.yorku.ca,orwithinansshsessionfromWindowsPowerShell, macOSTerminal,etc. c. Using an editor on your own personal computer that supports SFTP or equivalent(e.g.BBEdit,Textwrangler,EditPlus,etc.) Also, consider using Matlab/Simulink to simulate the any unfamiliar components or circuits before implementing the Verilog solution. The reason? A graphical tool like Simulink will help you lay out your parts and help you see how the system is supposed to work before writing up the text-based script. If something goes wrong you can look at Simulink to help debug and understand. Figure1UsinggraphicaltoolslikeSimulinkorMapleSimtoquicklyexamineyourcircuitaheadoftimeishelpful. EECS2021–LabJ:BuildaCPU2022 StudentVERSION The Lab This is continuation of the first Verilog lab. You can model the circuits in this lab using a number of different Verilog solutions, including 1. Theinternal(toYorkU)SSHorGUIinterfaceforremotelab.eecs.yorku.ca 2. Theexternal(toYorkU)commercialsystem,EDAPlayground (edaplayground.com) The methods for implementation are slightly different due to the nature of the interfaces, but they can produce the same results. Part 1: Looking at the MUX again. 1. In a previous lab we created the 2-to-1 mux shown in the left part of the figure below and found that it acts as an if statement. In this lab we will use abstraction to encapsulate this circuit as a reusable component so that it can be used by someone who doesn't know how it works internally. Let us adopt the diagram shown in the right part of the figure as an abstraction of what this circuit does: a box with two doors, labelled 0 and 1, and a control input c. The control is so named because it actually controls the circuit: if it is =0 then Door-0 would open and z would be a. Otherwise z would be b. We will call the component yMux1. 2. Either with the (a) command line version of iVerilog on RemoteLab or (b) with EDA Playground set to iVerilog, create the Verilog model file “program” yMux1.v as follows: // Import the Multiplexor (MUX) circuit // The yMux1.v file defines the module. It will be linked in. // yMux1 is a “type” defined in that file. // my_mux() is an instance of the type yMux1 // z is an output; a, b, and c are inputs to the mux. yMux1 my_mux(z, a, b, c); “Importing” an instance of a module. In your Verilog “test bench” file you can create an instance of the mux that has been defined in a separate file, yMux1.v. This is how you allow that mux to be tested within the test bench. See the EDA Playground screenshot below for placement within the test bench Verilog file. Compare this with the testing modules we wrote earlier. Note that the circuit's ports are listed in the module statement and that a special declaration is used to indicate their “in” or “out” status. Note also the absence of any initial block. In a way, this Figure2Ifyou'reusingEDA Playground,pressthe"+"symbolto createanewfile. EECS2021–LabJ:BuildaCPU2022 StudentVERSION module to a testing module is like a library class to an app with a main method. 3. Using Part 8 of Lab I as your starting point, create the program LabJ.v that instantiates and tests yMux1. Treat this component the same as a built-in one. Include a testing regime. How to test? You can do a) manual testing, b) via command-line arguments, or c) an exhaustive, three-nested-loop test (shown below in EDA Playground) Skip ahead if you’re using EDA Playground. If you’re running from the command line, compile your program using the command: 
 iverilog LabJ_part1.v This command searches for a module that defines yMux1 and compiles it, together with LabJ_part1.v, to produce a single executable file named a.out. Alternatively, you can specify the names of the needed modules explicitly on the command line: 
 iverilog LabJ_part1.v yMux1.v 4. 
Run the model. If you’re using the command line, use vvp to run your Verilog model “program” and ensure that the multiplexor (“mux”) module behaves as expected. You can also use EDA Playground to run the simulation: Figure4RatherthanusethecommandlineyoucanuseEDAPlaygroundtoexaminethemux,evenifyouhavethe muxdefinedinaseparatefile,asshownhere.Weuseathreelevellooptorunthe“exhaustivetesting”. Figure3Youcandocommand-linearguments inEDAPlayground,too.Forinstance,inthis example,puttheargumentsintheRunboxlike this:a.out+a=1+b=0+c=0 EECS2021–LabJ:BuildaCPU2022 StudentVERSION Part 2: Combine two Mux’s to control a “Bus” What if, with a single command signal, c, you could control the flow of two different output signals, z0 and z1? You can! Given that one mux can control the flow of one signal, if you have two mux’s, both connected to the same control signal, c, you can control the flow of signals into z0 and z1 at the same time. For instance, if c is 0, then the first output wire z0 will output a0 and second output wire z1 will output a1. 5. We call a bundle of related wires a “bus”. As shown in Figure 5 we seek to enhance our mux so it can handle 2-bit busses instead of 1-bit wires, as
Answered 1 days AfterNov 29, 2022

Answer To: https://eclass.yorku.ca/pluginfile.php/4000486/mod_resource/content/2/LabK_EECS2021_VerilogLab4_F202...

Sukanya answered on Dec 01 2022
40 Votes
module yMux4to1(z, a0,a1,a2,a3, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0]
a0, a1, a2, a3;
input [1:0] c;
wire [SIZE-1:0] zLo, zHi;
yMux #(SIZE) lo(zLo, a0, a1, c[0]);
yMux #(SIZE) hi(zHi, a2, a3, c[0]);
yMux #(SIZE) final(z, zLo, zHi, c[1]);
endmodule
module yAlu (z, ex, a, b, op) ;
input [31:0] a, b;
input [2:0] op;
output [31:0] z;
output ex;
wire cout;
wire [31:0] alu_and, alu_or, alu_arith, slt, tmp;
wire [15:0] z16;
wire [7:0] z8;
wire [3:0]...
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