Homework Questions: Ch2a Group Information Number:_________ Name/email:___________________________________ Number:_________ Name/email:___________________________________ Number:_________ Name/email:___________________________________ Authors: Mark McKenney Organization: CS 516, Department of Computer Science, SIUE Concepts Caches work only because of locality of memory references. 1. Write a short code snippet the illustrates the concept of temporal locality of data. . . . . 2. Write a short code snippet the illustrates the concept of spatial locality of data (not instructions). . . . . 3. Does using multi-word blocks in cache take advantage of spatial or temporal locality? Explain why. . . . . 1 Direct Mapped Caching 1. Assume a direct mapped cache that can hold 2k (2048) words. Assume the cache has 1 word per block. (don’t forget dirty bits, valid bits, and tag bits). Draw a diagram of how 1 cache line is structured (similar to the diagrams in the slides that show the tag field, the data field, etc). Label each field with what it holds, and how many bits it requires. . . 2. Assume a direct mapped cache that can hold 2k (2048) words (as in the previous question). If the cache has 1 word per block, how many bits are required to implement the entire cache? (don’t forget dirty bits, valid bits, and tag bits). . . 3. Assume a direct mapped cache that can hold 2k (2048) words. Assume the cache has 8 words per block. (don’t forget dirty bits, valid bits, and tag bits). Draw a diagram of how 1 cache line is structured (similar to the diagrams in the slides that show the tag field, the data field, etc). Label each field with what it holds, and how many bits it requires. . . 4. Assume a direct mapped cache that can hold 2k (2048) words (as in the previous question). If the cache has 8 word per block, how many bits are required to implement the entire cache? (don’t forget dirty bits, valid bits, and tag bits). . . 2 5. Consider a direct mapped cache that holds 8 blocks, arranged with 1 word per block. For the following sequence of memory address references, indicate which are hits and which are misses. Assume the cache is word aligned (that is, ignore the 2 lowest order bits in the address). address binary representation hit or miss 12 44 20 56 24 44 48 52 60 58 6. Consider a direct mapped cache that holds 8 blocks, arranged with 4 words per block. For the following sequence of memory address references, indicate which are hits and which are misses. Assume the cache is word aligned (that is, ignore the 2 lowest order bits in the address). address binary representation hit or miss 12 44 20 56 24 44 48 52 60 58 Associative Caching 1. Assume an associative cache that can hold 2k (2048) words. Assume the cache has 1 word per block. Assume the cache has 2 sets (so each block of memory can show up in 2 possible locations in cache). (don’t forget dirty bits, valid bits, and tag bits). Draw a diagram of how 1 cache line is structured. (similar to the diagrams in the slides that show the tag field, the data field, etc). Label each field with what it holds, and how many bits 3 it requires. Note that even though there are 2 sets, you are only required to draw 1 line in 1 set. . . 2. Assume an associative cache that can hold 2k (2048) words and has 2 sets (as in the previous question). If the cache has 1 word per block, how many bits are required to implement the entire cache? (don’t forget dirty bits, valid bits, and tag bits). . . 3. Assume an associative cache that can hold 2k (2048) words. Assume the cache has 8 words per block. Assume the cache has 2 sets (so each block of memory can show up in 2 possible locations in cache). (don’t forget dirty bits, valid bits, and tag bits). Draw a diagram of how 1 cache line is structured (similar to the diagrams in the slides that show the tag field, the data field, etc). Label each field with what it holds, and how many bits it requires. Note that even though there are 2 sets, you are only required to draw 1 line in 1 set. . . 4. Assume an associative cache that can hold 2k (2048) words and has 2 sets (as in the previous question). If the cache has 8 word per block, how many bits are required to implement the entire cache? (don’t forget dirty bits, valid bits, and tag bits). . . 4 5. Consider as associative cache that holds 8 blocks, arranged with 1 word per block and 2 sets. For the following sequence of memory address references, indicate which are hits and which are misses. Assume the cache is word aligned (that is, ignore the 2 lowest order bits in the address). address binary representation hit or miss 12 44 20 56 24 44 48 52 60 58 6. Consider an associative cache that holds 8 blocks, arranged with 2 words per block and 2 sets. For the following sequence of memory address references, indicate which are hits and which are misses. Assume the cache is word aligned (that is, ignore the 2 lowest order bits in the address). address binary representation hit or miss 12 44 20 56 24 44 48 52 60 58 5