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Instruction Sets Memory Hierarchy Three of students has to have Presentation for three commercial CPUs in last week of November. · ARM: Aaron Linder · Motorola: Anthony Smith · Intel: Raj For above three commercial CPUs, you investigate in terms of · Register structure (Data register, Address register, Stack register if available) · Instruction Sets and their format · Directives · Show simple examples of the usage of instruction sets Compiler High-level Language Compiler Machine Language Scanner (Syntax error check) Parser (Semantic error check) Assembler (Assembly language) Code Optimizer (Optimized Assembly code) Code Generator (Machine language) Compiler Designer: · What kinds of instructions sets are available for the specific CPU of target machine? · How many address and data registers are available for the specific CPU? · Memory organization of target system · Data types supported by the target system Chapter topics: · How the memory is organized · How to define memory location · How the CPU accesses the memory CPU Main Memory Instruction Cycle: 1. CPU performs an Instruction Fetch (Instruction Fetch) 2. CPU decode the instruction and execute the instruction (Instruction Execution) In order to perform an instruction cycle, the given fetched instruction should provide at least four information to CPU. 1. Opcode: What CPU has to do EX) ADD, LOAD, MUL, SUB, LOOP, JUMP,….. 2. Operand: Which and what CPU has to add in case of ADD EX) ADD X Y X = X + Y 3. Destination Address: Where the CPU has to save the result EX) ADD X Y X = X + Y 4. Address of next instruction in main memory EX) This information is typically kept in a special register called Program Count (PC). CPU (R1, R2, ….) Main Memory X 3 Y 5 Z 2 High-Level Language vs. Assembly Language LOAD R1 X R1 = X X = X + Y; ADD R1 Y R1 = [R1] + Y MOVE R1 X X = [R1] In High-level language, we can use only simple algebra but in Assembly language, we need to express all data flow between CPU and main memory. So, the instruction sets have to provide operations with sufficient functionality to implement any high-level language expressions. · Data transfer operations (LOAD, MOVE) · Arithmetic operations (ADD, SUB, MUL, DIV) · Logic operations (AND, OR, XOR, EQ, NEQ, GT, LT) · Control operations (IF, BRANCH, GOTO) · I/O operations (READ, WRITE) LOAD R1 X ADD R1 Y MOVE R1 X vs. CLEAR R1 ADD R1 X ADD R1 Y MOVE R1 X Since the register R1 could have some garbage value, we need to clear and initialize the R1 first with “CLEAR R1”. · How the memory is organized · How to define memory location (Bit address, Byte address) · How the CPU accesses the memory (Direct, Indirect, Immediate and etc.) Bit Address: In case of 32-bit machine instruction It means one instruction size is 32-bit. Bit Address Value 0 0, 1, 2, …… 31 32 32, 33, 34, ….. 63 64 64, 65, 66, ….. 95 i i, i+1, i+2, ….. i+31 i+32 i+32, ….. i+64 Byte Address: (Actual addressing method adopted in contemporary computer systems) In case of 32-bit machine instruction It means one instruction size is 32-bit (4 bytes) Byte Address Value 0 0, 1, 2, …… 31 4 32, 33, 34, ….. 63 8 64, 65, 66, ….. 95 i i, i+1, i+2, ….. i+31 i+4 i+32, ….. i+8 Program Count (PC) register will point out the current location of the instruction on the main memory. In case of the sequence instruction with byte address, the PC will increase its value by 4 to point out location of the next instruction on the main memory. PC = i; PC = PC + 4; But, if the CPU meets some conditional branch instruction, the PC will not be sequentially increased by 4. Instead, it will decrease its value or jump to another address. Example) X = X + Y; Can be implemented with assembly language as follows. LOAD R1 X ADD R1 Y MOVE R1 X With the same logic, let us try to implement the following high-level program with assembly language. Sum = Num1 + Num2 + Num3 + ………… + NumN LOAD R1 Num1 ADD R1 Num2 ADD R1 Num3 ……. ADD R1 NumN MOVE R1 Sum Since the main memory is usually divided into two parts (Instruction part and Data part or Stack part), the above instructions will be loaded to Instruction part while data (Num1, Num2, Num3,…..,NumN) are loaded to Data part on the main memory. Main memory Address Value Instruction part Data part i LOAD R1 Num1 i+4 ADD R1 Num2 i+ 8 ADD R1 Num3 ….. i + 4N – 4 ADD R1 NumN i + 4N MOVE R1 Sum Num1 4 Num2 7 Num3 2 ….. ….. NumN 9 Sum X Y 1 i 2 i+4 3 i+ 8 N ????? This will follow the general form of linear function graph: Y = aX + b i = a + b --- (1) i + 4 = 2a + b --- (2) (2) – (1): 4 = a a = 4 If we plug “a = 4” to (1) i = 4 + b b = i - 4 Y = 4X + (i – 4) Y = 4N + (i – 4) = i + 4N - 4 We could implement the above example using a LOOP instruction. Main memory Address Value Instruction part Data part i LOAD R1 N i+4 CLEAR R2 i+8 (LOOP) Determine address of next input (Num1 is the first one) i+ 12 ADD the number R2 i+ 16 DEC R1 i+ 20 Branch > 0 LOOP i+ 24 MOVE R2 Sum Num1 4 Num2 7 Num3 2 ….. ….. NumN 9 Sum Notes: · DEC R1 R1 = R1 – 1 · In address “i+20”, Branch > 0 LOOP If R1 > 0, PC = LOOP Otherwise, PC = i+24