Computer Architecture Question
Extracted text: Reset Help 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 38 40 41 42 45 46 47 63 64 68 128 158 222 Cache m C B E S b 1. 32 1,024 4 4 64 18 6 8 2. 32 1,024 4 256 24 8 3. 32 1,024 8 1 128 18 7 7 4. 32 1,024 8 128 1 24 1 7 5. 32 1,024 32 1 32 22 5 1,024 8 6. 32 32 4 24 3 5 You labeled 9 of 24 targets incorrectly.
Extracted text: The following table gives the parameters for a number of different caches. For each cache, fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Drag the appropriate labels to their respective targets. Reset Help 2 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 38 40 41 42 45 46 47 63 64 68 128 158 222 Cache m C В E S 1. 32 1,024 4 4 64 18 6 1,024 24 2. 32 4 256 8 3. 32 1,024 8 1 |128 18 7 7 1,024 1 4. 32 8. 128 24 7 5. 32 1,024 32 1 32 22 5 1,024 24 6. 32 32 4 3 5