Introduction to VLSI Design (EECE 6080C) Ranga Vemuri Home Work - 1 In the following, you will use an n-well CMOS process where the minimum feature size is set to 0.6 microns. All dimensions should be...

simulate and get results in hspice and IRSIM


Introduction to VLSI Design (EECE 6080C) Ranga Vemuri Home Work - 1 In the following, you will use an n-well CMOS process where the minimum feature size is set to 0.6 microns. All dimensions should be multiples of 0.3 microns. Spice and IRSIM model files are available to you via the Canvas system. Make sure to include appropriate diffusion areas and perimeters for all transistors in all circuits. 1. Using Spice, experimentally demonstrate that the n-transistor is a good conductor of logic Low and a poor conductor of logic High and that the p-transistor is a poor conductor of logic Low and a good conductor of logic High. Experimentally show how the T-gate overcomes these limitations. Submit the relevant source files, date, waveforms, observations and comments. 2. Using Spice, simulate a static CMOS inverter with the lengths and widths of both transistors set to the minimum dimensions allowed by the technology. Measure the rise time and fall time when a pulse input is applied. Now increase the width of the p-transistor so that the rise time becomes equal to the fall time. We will call the inverter so sized, the reference inverter. Determine the rise and fall times of the inverter and measure (Tr and Tf). Determine propagation delays TpLH, TpHL and Tp. Submit the Spice file and the waveforms showing the input pulse, output rise and output fall, clearly mark the rise/fall measurements and report the transistor dimensions. Report the propagation delays. 3. Resize the inverter such that the rise time and fall time are equal and propagation delay is Tp/k, for k = 1, 2, 4, 6, 10. Keep the lengths of transistors at the minimum values. Plot Delay vs. Wp/Wn. Submit the Spice files and the waveforms showing the input pulse, output rise and output fall, clearly mark the rise/fall measurements and submit the Delay vs. Wp/Wn plot. What do you learn from this plot? 4. Connect a 80fF capacitor at the output of the reference inverter and determine the propagation delay of the inverter. Submit the waveforms showing the input pulse, output rise and output fall and clearly mark the rise/fall measurements. Report the propagation delays. Adjust the transistor sizes such that the worst case propagation delay is equal to that of the reference inverter designed in the previous step. Submit the Spice file and the waveforms showing the input pulse, output rise and output fall and clearly mark the rise/fall measurements. What do you learn from this experiment? 5. Design a static CMOS gate for the ex-or function assuming that the inputs are available in both uncomplemented and complemented forms. Simulate using the Spice simulator. Attach a 80 fF capacitor at the output and adjust the sizes of the transistors such that the worst case propagation delay is equal to that of the reference inverter designed in the previous step. Draw the circuit and note the values of W’s and L’s next to each transistor. Also, submit the Spice file for the circuit and a plot of the simulation waveforms with comments. Simulate the same sized circuit using IRSIM and submit the simulation waveforms and IRSIM circuit file. Compare and comment on the simulation results when using Spice vs. IRSIM. Summarize what you have learned from this exercise. Your entire submission should be a single .pdf file submitted via Canvas. In addition, submit a hardcopy in the class, at the beginning of the class time.