Simulation. As an alternative to tagging requests and replies on a split-transaction bus, a bus can be designed so that the replies are forced to occur in the same order as the requests. Thus, each reply can be identified by its position in the stream of replies. Suppose the delay of a transaction is uniformly distributed between 1 and Tmaxcycles. Use simulation to compare the average latency of a tagged bus and an ordered-reply bus.
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