Suppose 1.0-V CMOS is fabricated using 0.25-mm technology and t OX = 8 nm. Consider inverters with L N = 0.25 μm, W N = 1.0 μm, L P = 0.25 μm, and W P = 2.5 μm. 1. Calculate and plot the propagation...

Suppose 1.0-V CMOS is fabricated using 0.25-mm technology and t_OX
= 8 nm. Consider inverters with L_N
= 0.25 μm, W_N
= 1.0 μm, L_P
= 0.25 μm, and W_P
= 2.5 μm.

1. Calculate and plot the propagation delay (assuming 20 on-chip loads) vs. the threshold voltage (0.1 V ≤ V_T
≤ 0.6 V).

2. Calculate and plot the standby dissipation vs. the subthreshold voltage (0.1 V ≤ V_T
≤ 0.6 V). Assume the subthreshold conduction is dominant with S = 100 mV.