Suppose that two CMOS inverters are connected in an inappropriate attempt at wired logic, as shown in Figure XXXXXXXXXXK = 0.5 mA/V 2 , V T = 0.5 V, and V DD = 3.3 V. 1. Determine the resulting value...

Suppose that two CMOS inverters are connected in an inappropriate attempt at wired logic, as shown in Figure 13.33. K = 0.5 mA/V², V_T
= 0.5 V, and V_DD
= 3.3 V.

1. Determine the resulting value of supply current if the input to one gate is grounded while the input of the other gate is connected to V_DD.

2. Compare this level of current to the peak current under normal operation of the CMOS gate.

Figure 13.33