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The objective of this lab is to design an Arithmetic and Logic Unit (ALU) using VHDL, specifically the ALU should be defined using the behavioral model. The ALU is illustrated in Figure 1, and the specification for the instructions to implement are included in Table 1.

Answered Same DayJan 23, 2021

Answer To: p.p1 {margin: 0.0px 0.0px 0.0px 0.0px; font: 12.0px Cambria; min-height: 14.0px} p.p2 {margin: 0.0px...

Kshitij answered on Jan 28 2021
142 Votes
Screenshoot.docx
Screenshoot
    
ALU VHDL CODE
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:31:34 01/26/2020
-- Design Name:
-- Module Name: alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Des
cription:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port (A : in std_logic_vector(31 downto 0); -- Vector of 32 bits
B : in std_logic_vector(31 downto 0); -- Vector of 32 bits
ALUCntl : in STD_LOGIC_VECTOR (3 downto 0); -- Vector of 4 bits
         Overflow : out std_logic;
         Carryout : out std_logic;
         ALUout : out std_logic_vector(31 downto 0));
        
end alu;

architecture Behavioral of alu is
signal Carryin: std_logic_vector(32 downto 0);
begin
process(A, B, ALUCntl,Carryin)
begin
case ALUCntl is
when "0000" =>
ALUout<= A and B; --AND
when "0001" =>
ALUout<= A or B;
         when "0011"=>
         ALUout<=A xor B;
         when "0010"=>
         Carryin<="0"&A +B;
         ALUout<= Carryin(31 downto 0);
         Carryout<=Carryin(32);
         when "0110"=>
         if(A>=B) then
         ALUout<=A-B;
             Overflow<='0';
             else
         ALUout<=A-B;
Overflow<='1';
end if;            
         when "1100"=>
         ALUout<=A nor B;
when others =>
NULL;
end case;
end process;
end Behavioral;
TEST BENCH VHDL CODE
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:01:17 01/26/2020
-- Design Name: alu
-- Module Name: tb_alu.vhd
-- Project Name: alu_project
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_alu_vhd IS
END tb_alu_vhd;
ARCHITECTURE behavior OF tb_alu_vhd IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT alu
    PORT(
        A : IN std_logic_vector(31 downto 0);
        B : IN std_logic_vector(31 downto 0);
        ALUCntl : IN std_logic_vector(3 downto 0);
        Overflow : OUT std_logic;
        Carryout : OUT std_logic;
        ALUout : OUT std_logic_vector(31 downto 0)
        );
    END...
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