Last Name:_____________________First Name:_____________________Total [200]: _________________________[Attention:Everything should be written in your own words. Any violation will receive 0 for...

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There is a section where you have to make a video. Please don't make the video, I will make the video myself. I have added two papers. You can choose from any one of these.


Last Name:_____________________ First Name:_____________________ Total [200]: _________________________ [Attention:Everything should be written in your own words. Any violation will receive 0 for this assignment.] Points Comments Introduction/Motivation [30] Related work [80] including design, evaluation, and significant Results for each paper. Conclusions and future work [20] Reference [10] Presentation [30] Video [30] COSC 5310 Advanced Computer Architecture Jiangjiang (Jane) Liu NOTE: · Do not include student ID in any submissions. · Survey should be written in your own words. (Any violation will receive 0 for this assignment.) · All files should be uploaded one by one, no zip. · Any course related-topic of your interest. Survey Write a survey (Microsoft WORD), presentation (Microsoft PowerPoint) and a video of your presentation based on the 5-6 Computer Architecture papers focusing on one topic of your interest. You can Search Conference Papers in Digital Libraries: www.lamar.edu--> Library --> Database List --> ACM Portal IEEE Explore Topics or other Computer Architecture (CA)-related topics of your interest (make sure it is related to Computer Architecture): Cloud Computing+CA, ML/AI+CA, IoT+CA, Big Data+CA, scalability, reliability, security, etc. Survey: The survey should have the following information. · Title · Introduction/Motivation · Related work with brief overview of design, evaluation, and significant results for each paper. · Conclusions and future work · Reference Conferences or other conferences of your interest: · ACM International Symposium on Computer Architecture e.g. https://www.iscaconf.org/isca2022/program/ · IEEE International Symposium on High Performance Computer Architecture e.g. https://hpca-conf.org/ · Supercomputing e.g. https://sc22.supercomputing.org/ Presentation: The presentation should include the following information related to your selected topic. Each paper has about 3 slides. · Introduction/Motivation · Related work with brief overview of design, evaluation, and significant results for each paper. · Conclusions and future work · Reference Video: The video should be about 10-15 minutes with a brief introduction of yourself and the presentation. What to submit: Submit files one by one. Do not zip files. · Survey (Word File with Reference) · Survey Format (optional): Selected conference information, URL, and required conference paper format for authors. · Presentation (PowerPoint File) · Video (video.mp4) · Papers (PDF files) Requirement: ·All assignments should be typed in Microsoft WORD/PowerPoint file. ·Handwritten assignments will not be accepted. ·You should have a cover page with course code, student name, date, and instructor name. A Microprocessor-Based Virtual Mamory System ~. D. Ruggiero and S. G. Zaky Department of Electrical Engineering University of Toronto Toronto, Ontario, Canada ABSTRACT This paper presents a virtual memory system which may be connected to the memory bus of a ~st computer. The system is based on the use of a separate processor to interface to the backing store and perform all the processing re- lated to managing the virtual memory. The pro- posed approach provides a virtual memory that is transparent to the host processor, with one ex- ception. When a memory reference generated by the host results in a page fault, a long delay is encountered. This delay corresponds to the time taken by the virtual memory controller to carry out a page transfer. A prototype system based on the above ap- proach has been constructed. Bubble memory dev- ices are used to implement the backing store. Tne suitability of bubble memories in this envi- ronment is discussed in the paper. Keywords: Virtual Memory, Memory Management, Ar- chitecture of Sm~ll Computer Systems, Mi- croprocessor Applications, Bubble Mamories. I. INTRODUCTION Progress in the areas of computer architec- ture and LSI technology is quickly removing some of the limitations on the performance of mini- and microcomputers. One of the se@erest res- trictions found in small computers is the lim- ited address space resulting from a short word length. Memory management schemes that allow a much larger address space - 4 million words or more - are now available for most minicomputers and many of the new 16 bit microprocessors. Despite the continuous drop in the cost of semi- conductor memory, it is not economically feasi- ble to provide such a large random access me- mory. Block accessed serial memories are typi- cally an order of magnitude cheaper per bit, and thus can readily provide the required memory si ze. This work was sponsored by the National Sciences and Engineering Research Council of Canada under research grant A8994. The utilization of a serial memory as sto- rage for a mini- or microcomputer faces only one obstacle: for a variety of reaso.qs, serial dev- ices are not directly suitable for program sto- rage. The solution to this dilemma has been known in large computer systems for some time[l,2]. It consists of using serial, block- accessed devices together with a limited anount of RAM in a virtual memory scheme. Virtual memory approaches have not been used in small computer systems because the com- plexity of the control needed to make such a system function requires extensive redesign of existing CPUs. Attempts to apply virtual memory to existing microprocessors have resulted in li- mitations being imposed on the host processor[3]. For example, several instructions could not be used because of the effect of page faults on their execution. Furthermore, multi- word instructions could not be broken over a page boundary. This paper presents a virtual memory system in which an independent processor is employed to perform all the management functions. These functions include address calculations, keeping and updating of page tables, execution of trans- fers between RAM and mass storage, as well as implementation of the details of the replacement algorithms. The system is intended to be con- nected to the memory bus of a host processor. At its interface to the bus, it appears as a large random access memory. Internal details of the virtual memory organization and management are transparent to the host. The paper dis- cusses the architectural features that the host processor must have in order for this approach to be feasible. A prototype of the proposed virtual memory system has been constructed, using bubble memo- ries to implement the backing store. Electrome- chanical media, e.g. tapes, disks, and drums, have traditionally dominated the field of serial memories. However, the technology of solid state serial memories offers a viable alterna- tive, particularly in small systems. Bubble me- mories and charge-coupled devices are likely to play a larger role in computer systems of the near future. For example, reliability and the absence of moving parts make such memories at- tractive in portable and airborne applications. If the anticipated reductions in cost per bit materialize, bubble memories could become cost- effective in general purpose systems. Some of the merits and limitations of bubble memories in a virtual memory environment are discussed la- ter. CH1494-4/80/0000-0228 $00.75 © 1980 IEEE 228 http://crossmark.crossref.org/dialog/?doi=10.1145%2F800053.801930&domain=pdf&date_stamp=1980-05-06 2. DESIGN PHILOSOPHY The structure of the proposed virtual me- mory system is shown in Fig. I. The Virtual Me- mory Controller (VMC) performs two major func- tions: I. Translation of addresses generated by the host to physical RAM addresses. Address translation is carried out whenever the host issues a memory re- quest with an address that corresponds to a page currently residing in the RAM. 2. Transfer of a page of data from the mass storage device to the RAM when the page referenced by the host does not reside in the RAM. HOST PROCESSOR MASS STORAGE I MEMORY BUS I VIRTUAL MEMORY CONTROLLER (VMC) RAM Figure I: Organization of the Virtual Memory System The above two functions have sufficiently dif- ferent time scales that they must be handled differently. The host must be allowed fast ac- cess to pages which reside in the RAM. This me- ans that it is not feasible for the VMC micro- processor to handle individual memory cycles. Hence, memory references to pages that are resi- dent in the RAM are handled directly by the ad- dress translation hardware in the VMC. The mi- croprocessor is called upon only when a page fault occurs. It then finds a page frame in the RAM which can be used, stores its contents in the backing store, if necessary, and transfers the new page from the backing store to the RAM. ]he host memory request which resulted in the page fault is serviced once transfer of the new page is complete. The use of a separate and independent pro- cessor to perform the management functions in the virtual memory system leads to several ad- vantages. The host processor is relieved of all knowledge of the internals of the memory system: it need not concern itself with the management of the available RAM or with the details of page tables and address calculations. This scheme also relieves the host processor of the need to control mass storage devices directly, since the VMC processor can take on this function. Another important advantage of the dedicated processor approach is to allow the implementa- tion of a large variety of alternative replace- ment algorithms easily and efficiently. The ease of implementation results from having the details of the algorithm localized in the VMC processor; efficiency is gained because it is possible to have the VMC processor perform parts of the algorithm concurrently with the host pro- cessing. This allows shorter sequences when a page fault occurs and consequently greater ove- rall memory speed. 3. HOST ARCHITECTURE The virtual memory sy&tem described in this paper was intended to be completely transparent to the host processor. Transparency can be ac- hieved provided that certain requirements are satisfied by the host architecture. This is discussed below in some detail. 3.1 WAIT STATE As described, the virtual memory system emulates the characteristics of a RAM, with the exception that some memory references are ex- tremely slow. A slow reference results when a page fault occurs and a subsequent transfer of data between mass storage and RAM takes place. In order to handle this situation, the host may simply be forced to wait umtil the page transfer is completed. This is feasible provided that operation of the host can be suspended in the middle of an instruction. Examples of such pro- cessors are the Intel 8080, 8085, and 8086 fami- lies of microprocessors, which can stay indefin- itely in a Wait state during any mamory cycle. The Zilog Z8000 and Motorola MC68000 also allow an indefinite Wait state. 229 Not all processors are capable of an inde- finite Wait. In the case of the Kotorola M6800, for example, a memory cycle can be extended by stretching phase I of the processor clock to a maximum of about 4~s. Extending the wait per- iod beyond this length leads to loss of informa- tion due to the dynamic nature of storage on the microprocessor chip. The period required to process a page fault depends on several factors, but primarily on the page size and the type of mass storage used. With present technologies this time is at least an order of magnitude lon- ger than the above 4~s, even for very small page sizes. Therefore the above approach is not suitable for use with dynamic processors that do not have an indefinite Wait capability. The fact that the processor can be halted between instructions is of no use in a virtual memory system, since page faults will occur during either the fetch or execution phase of an in- str uc tion. point 2 is difficult to implement without chang- ing the structure of the host. Consider for ex- ample the case of a PDP-11 processor. The pro- gram counter is incremented as successive words of a multiple word instruction are fetched. Thus, at the time of a page fault, the starting address of the instruction that caused the fault is not known. Furthermore, because of the au- toincrement and autodecrement features, the con- tents of one or more registers may have been al- tered. It is very difficult for a device other than the host rocessor to perform the roll-back function. Such a capability can be implemented as an integral part of the design of the host. However, it requires that the host CPU be de- signed with virtual memory in mind, which pre- cludes the use of virtual memory with many ex- isting processors. 3.2 TIM£ OUT Processors that use a time-out mechanism to
Answered Same DayFeb 23, 2023

Answer To: Last Name:_____________________First Name:_____________________Total [200]:...

Shubham answered on Feb 23 2023
32 Votes
Paper 1
Title
Security Challenges in Embedded Systems
Introduction
Embedded systems are increasingly being used in critical applications such as automotive, healthcare, and aerospace, making their security a top priority. However, these systems pose unique challenges, including limited resources, real-time constraints, and diverse hardware and software configurations. This article reviews recent research o
n security challenges in embedded systems and proposes future directions for addressing them.
Related work
The paper proposes a secure update mechanism that ensures integrity and authenticity of firmware updates, even in the face of adversarial attacks. The authors evaluate their approach on an AVR microcontroller and demonstrate its efficacy in preventing attacks such as buffer overflow and code injection.
The authors describe a memory isolation scheme that prevents unauthorized access to critical system components. They use hardware-enforced memory protection and evaluate their approach on an ARM Cortex-M3 microcontroller, showing that it incurs only a small performance overhead.
The paper highlights a security framework that includes secure boot, secure communication, and intrusion detection mechanisms (Serpanos & Voyiatzis, 2013). The authors evaluate their approach on an AUTOSAR-compliant embedded system and demonstrate its effectiveness in detecting and mitigating attacks.
Conclusions and future work
Embedded systems are becoming increasingly prevalent in critical applications, making their security a top priority. The papers reviewed in this article propose various approaches for securing these systems, including secure firmware updates, memory isolation, and intrusion detection mechanisms. Future work should focus on developing more comprehensive security frameworks that take into account the unique challenges posed by embedded systems, including limited resources and diverse configurations. Additionally, research should continue to explore the effectiveness of these approaches in mitigating attacks and improving overall system security.
Paper 2
Title
Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas
Introduction
Embedded systems and Field-Programmable Gate Arrays (FPGAs) are crucial components of modern computing devices, including Internet of Things (IoT) devices, automotive, and aerospace systems. However, these systems are vulnerable to security threats due to their limited resources, low-cost design, and distributed deployment. Multi-tenant FPGAs, which are shared among multiple users, pose additional security challenges, including resource contention, access control, and information leakage. In this paper, the authors address these security challenges by proposing a set of solutions for embedded systems and multi-tenant FPGAs.
Related work
The paper builds on the existing literature on security challenges in embedded systems and multi-tenant FPGAs. The authors review previous studies on security threats and mitigation techniques, including hardware-based security mechanisms, access control, and encryption. The authors also investigate the existing approaches to address the security challenges in multi-tenant FPGAs, such as virtualization, partitioning, and dynamic resource allocation.
The paper proposes a comprehensive security framework for embedded systems and multi-tenant FPGAs. The framework includes several hardware and software components, including secure boot, access control, encryption, and dynamic resource allocation (Provelengios, 2021). The authors evaluate the proposed framework using a set of experiments on a testbed consisting of different types of embedded systems and multi-tenant FPGAs. The results show that the proposed framework is effective in mitigating various security threats, such as denial-of-service attacks, side-channel attacks, and information leakage.
The paper provides a set of solutions to address the security challenges in embedded systems and multi-tenant FPGAs. The proposed security framework offers a comprehensive set of hardware and software components that can be...
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