This is a MIDTERN of ECE (Computer engineer) The class is called Computer Architecture mainly deal with CPU and the coding language is VHDL. The attached PDF is the past midterm. There will be 5...








This is a MIDTERN of ECE (Computer engineer) The class is called Computer Architecture mainly deal with CPU and the coding language is VHDL. The attached PDF is the past midterm. There will be 5 questions. The question 1 4 5 will be very similar and question 2 3 will be new question. The test will be hold at
6:30 - 8:30 PM on Thursday, April 29th EST.
If you take my order, there will be several PDF of the lecture. This is a two hour exam. The professor will email me the exam paper at 6:30pm and we have two hours to do it.



Microsoft Word - Exam_545_20.doc Accurately Print Your Name________________________Sign Your Name________________ ESE 545 Prof. Mikhail Dorojevets Spring 2020 Mid-term Exam Monday, April 20 5:30:6:50 PM Open Book Closed Friends You have 5 questions (50 points total). 1. (9 points) We have a pipelined processor microarchitecture with a branch prediction rate of 80%. Only mispredicted branches have a penalty. The processor has the average CPI of 1.3 (that includes the CPI impact of branch prediction/misprediction). We know that 15% of executed instructions are branches. Someone proposed a change by decreasing the branch misprediction penalty by 3 cycles, but at a cost of increasing the clock cycle time by 5% for all instructions. What would be the percentage gain/loss in performance due to the proposed change to the microarchitecture? Say exactly gain or loss and calculate how much! ESE 545 Prof. Mikhail Dorojevets Spring 2020 2. (6 points) Select the single architectural technique that will most improve the performance of the code below. Briefly (one-two sentences) explain your choice, including description of why the other techniques will not improve performance as much and your assumptions about the machine design. The techniques you have to choose from are: out-of-order issue with register renaming, branch prediction, and superscalar execution. Loads are marked whether they hit or miss in the cache. 2(a) loop: ADD R3, R6, R2 LD R6, 8(R6) # cache hit BNEQZ R6, LOOP Circle one: • Out-of-Order Issue with Register Renaming (single instruction issue) • Branch Prediction • Superscalar with multiple-instruction issue 2(b) LD R1, 0(R2) # cache miss XOR R2, R1, R1 LD R1, 0(R3) # cache hit LD R3, 0(R4) # cache hit SUB R3, R1, R3 ADD R1, R2, R3 Circle one: • Out-of-Order Issue with Register Renaming (single instruction issue) • Branch Prediction • Superscalar with multiple-instruction issue 2(c) ADD.D F0, F1, F8 SUB.D F2, F3, F8 MUT.D F4, F5, F8 DIV.D F6, F7, F8 Circle one: • Out-of-Order Issue with Register Renaming (single instruction issue) • Branch Prediction • Superscalar with multiple-instruction issue ESE 545 Prof. Mikhail Dorojevets Spring 2020 3. (9 points). Mark whether the following modifications will cause each of the three categories to increase, decrease, or whether the modification will have no effect. Briefly explain your reasoning to receive credit! Assume the initial machine is pipelined. Also assume that any modification is done in a way that preserves correctness and maintains efficiency, but that the rest of the machine remains nchanged. Instructions/Program Cycles/Instruction Clock Cycle Time a Remove hardware floating-point instructions and instead use software subroutines for floating-point arithmetic b Improve branch predictor accuracy c Change load/store instructions to only use the address in a register (i.e., no offset) Instructions/Program Cycles/Instruction Clock Cycle Time d Add a single- lane vector unit. e Add fine-grain vertical multithreading and run a workload consisting of multiple separate single-threaded programs (multiprogram ming) f Add fine-grain vertical multithreading and run a workload consisting of single programs that have been parallelized (multithreading) ESE 545 Prof. Mikhail Dorojevets Spring 2020 4. (12 points) Assume that you have an advanced 2 GHz vector computer (shown as RV64V in Figure 4.1) with vector chaining implemented in hardware. The vector computer set of units, maximum vector length, and timing characteristics of its vector functional and load/store units are the same as those quoted in the textbook. (p. 292). Here is the code for this computer: LAB: LV V1, R3 ADDSV V2, F0, V1 MULTSV V3,F1, V1 SUBV V5,V2,V3 DIVSV V6,F2,V5 ADDV V4,V2,V6 SV V4, R3 SUBI R3,R3,8 BNEZ R3, LAB 4.1 Specify exactly how many convoys and show the convoys of vector instructions (not including any other (scalar) instructions!) for the above code. (You may draw lines to show the convoys on the existing code shown above.) 4.2 Show the execution time in clock cycles of this loop with n elements (Tn); assume Tloop = 15. Show the equation, and give the value of execution time for n=400. 4.3 What is the floating-point peak performance (R) for this loop? (Do not forget that only arithmetic floating-point operations need to be counted when calculating R!) ESE 545 Prof. Mikhail Dorojevets Spring 2020 5. (14 points) Show the overall picture of the memory hierarchy going from a 50-bit virtual address to a 36-bit physical address with two levels of cache in a way similar to the one shown in Figure B.17 but with additional details (see below). The structure, comparators and multiplexors (including the ones to choose byte/word sent to CPU), all fields (including valid bits but no access control bits), field widths, and the number of entries in the TLB, L1 and L2 cache must be specified in your diagram! Assume the following parameters:  The page size is 2 KByte.  The TLB is a 4-way set-associative. It has 512 entries (total).  The 4 KByte L1 write-through cache size is 2-way set-associative, virtually indexed, physically tagged.  The 1 MByte L2 write-back cache is 4-way set-associative.  The block size for both L1 and L2 caches is 256 bytes.
Apr 27, 2021
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