Thursday, Dec. 8,2022,12:00–3:00 p.m.
It will be remote. Available to take any time from 12:00 pm but must be submitted before 3:00 pm. Exam duration: 100 mins(expected)
Von Neumann and RISC-V Side Note Really need to get into RISC-V ! Getting waylaid by floating point Will come back to it later The von Neumann Model Memory: holds both data and instructions Processing Unit: carries out the instructions Control Unit: sequences and interprets instructions Input: external information into the memory Output: produces results for the user ‹#› The Stored Program Concept ‹#› It is the basic operating principle for every computer. It is so common that it is taken for granted. Without it, every instruction would have to be initiated manually. The stored program concept says that the program is stored with data in the computer’s memory. The computer is able to manipulate it as data—for example, to load it from disk, move it in memory, and store it back on disk. Program: A sequence of individual instructions aimed at collectively executing a specific task, e.g. Find the largest number in a set, Find out how many times the word “happy” appears in a text, etc… About the instructions Each instruction is a sequence of 1s and 0s (remember a computer cant understand except for logic High or Low) In RISC-V, the length of this sequence is fixed. It is 32 bits For example, addi t1, zero, 548 - 0x20090224 Literal meaning: “ Add the value contained in register 0 with 548, then put the addition result in register t1” Registers are temporary placeholders for data which is operated on by ALU(Arithmetic Logic Unit) The actual 32 bit instruction: 0010 0000 0000 1001 0000 0010 0010 0100 Please do not get intimidated by this sequence of 1s and 0s! The decoding of it back into a human understandable instruction is the focus of CSE120 How to store the instructions? In stored program machine, we need to keep track of where we place the instructions in main memory. Main memory is where all your computer’s data and instructions ultimately reside Main memory is not the only memory component in the computer. We also have the registers (faster and smaller memory units as well) How to store the instructions? Main Memory - Your Home Neighborhood analogy Imagine each instruction is located in a specific address in a neighborhood I1 I2 I3 1156 High St, Santa Cruz 700 Front St, Santa Cruz 220 Sylvania Ave, Santa Cruz If you want to fetch and execute instructions I1, I2, I3 in sequence, then you will need to sequentially travel to the addresses : 1156 High St -> 700 Front St -> 220 Sylvania Ave The same exact principle lies in storing program instructions in main memory as well We assign each of them addresses. Since data (which we will need to operate on) is also contained in main memory, they are referred to by their address in main memory as well The von Neumann Model Memory: holds both data and instructions Processing Unit: carries out the instructions Control Unit: sequences and interprets instructions Input: external information into the memory Output: produces results for the user ‹#› von Neumann Model - Memory Each location has an address and contents Address: bit pattern that uniquely identifies a memory location Contents: bit pattern stored at a given address. Analogy: P.O. boxes have fixed numbers, but changing contents. ‹#› von Neumann Model – Memory (2) Addressability (Byte vs. Word): a word is the basic unit of data used by the processing unit of MIPS 1 byte = 8bits ; 1 B= 8b 1 word = 4 bytes ; 1 word = 4B= 32b 1 halfword=2 bytes=16b 1 doubleword = 8 bytes = 64b Frequently, an instruction must store or retrieve an entire word with a single memory access. Addressability refers to the number of bytes of memory referenced by a given address. RISC-V machine is Byte Addressable ‹#› Byte addressability The memory is said to be byte addressable if the smallest unit of memory that can be addressed is 1 byte of memory 0xAB 0x00 0x20 0x03 0xFF 0x14 0 1 2 3 4 5 Consider the toy example below: Main memory capacity is 6 bytes and it is byte addressable Mem[0]=0x14 , i.e. 1416 = 0001 0100 in binary Mem[1]=0xFF , i.e. FF16 = 1111 1111 in binary Mem[2]=0x03 , i.e. 316 = 0000 0011 in binary Assume in example, that all the data (both instructions and operable data) are only 1 byte long. (More complex cases later!) Address Main Memory content Memory alignment Keep in mind that RISC-V memory is byte-addressable, so an actual RISC-V instruction(32-bit= 1 word long) actually occupies four contiguous locations (bytes) of main memory. Address01234567891011 8-bit data Word 1Word 2Word 3 The RISC-V architecture requires instruction words to be aligned in memory; 32-bit instructions must start at an address that is divisible by 4. 0, 4, 8 and 12 are valid word addresses. 1, 2, 3, 5, 6, 7, 9, 10 and 11 are not valid word addresses. Unaligned memory accesses result in a bus error This restriction has relatively little effect on high-level languages and compilers, but it makes things easier and faster for the processor hardware. ‹#› von Neumann Model – Processing Unit Does the actual work! Can consist of many sub-units, each specializing in one complex function. At a minimum, has Arithmetic & Logic Unit (ALU) and General Purpose Registers (GPRs) 4 - ‹#› ‹#› von Neumann Model – Processing Unit (2) ALU Performs basic operations: add, subtract, and, not, etc. Generally operates on whole words of data. Some can also operate on subsets of words Registers Fast “on-board” memory for a small number of words. Invaluable for intermediate data storage while processing Close to the ALU (much faster access than RAM). 4 - ‹#› ‹#› von Neumann Model – Control Unit The control unit coordinates all actions needed to execute the instruction It fetches & decodes each instruction, and sets up the appropriate inputs for the Memory, Processing, and I/O units as required. It communicates with memory via the Program Counter (PC) PC (aka Program Counter) Holds the address of the current instruction being fetched as well as cognizant of the address of the next instruction to be fetched into computer. ‹#› Notations Sets of Bits A[3:0] denotes a set of 4 bits: A3, A2, A1, A0 The content of an n-bit register Rx is referred to as Rx[n-1:0] RXn-1 is the most significant bit (MSB), or leftmost bit RX0 is the least significant bit (LSB), or rightmost bit Given RX[31:0], RX[7:4] refers to the four bits from RX7 down to RX4 Bit Assignment R2[5:0] ⇐ R1[13:8] Means that bits 5 to 0 of register R2 get assigned the values of bits 13 to 8 of register R1. Contents Mem[loc] means “content of memory location loc” (i.e., loc is the address) [Reg1] means the “contents of memory at address in Reg1” ‹#› von Neumann Model – Input/Output Generically known as peripherals - not in the sense that they matter less, but because they are external to the CPU. This means we will have to develop mechanisms for autonomous devices to communicate with each other - more on this later. 4 - ‹#› ‹#› Von Neumann and RISC-V IMPORTANT!! Please Pay Attention to emails you receive from this course’s Piazza site! Important information is often emailed from Piazza It is completely YOUR responsibility to keep track of any important email announcement on Piazza so that you do not lose any chance of getting a better final grade RISC-V Memory (RV64I) The particular flavor of RISC-V architecture we will be dealing with is RV64I The registers(that are used to temporarily hold data for ALU operations) are all 64-bits long. PC(Program Counter) is 64-bits long as well. 64-bit memory model An Address for locating any item(Instruction/Data) is 64 bits long Address 0x0000000000000000 to 0xFFFFFFFFFFFFFFFF How much memory is that? Origin of the word “Endian” One of the earliest literary instances of “satire” conflict between 2 groups of Lilliputians divided into those breaking the shell of a boiled egg from the big end or from the little end. Gulliver called them the "Big-Endians" and the "Little-Endians" Little Endians Big Endians break the shell of a boiled egg from the little end! break the shell of a boiled egg from the big end! Endianness Big Endian: Most significant byte occupying lower address position Little Endian: Least significant byte occupying lower address position ‹#› Endianness: Memory aid for exams Little Endians Big Endians Least significant byte of data occupies lower address position in memory! Most significant byte of data occupies lower address position in memory! Lol ‹#› Class Question Given the following byte addressable word aligned main memory: Assume Big Endian ordering, Then what is the word stored at mem[44]? 2. Assume Little Endian ordering, Then what is the word stored at mem[44]? Little Endians Least significant byte of data occupies lower address position in memory! Big Endians Most significant byte of data occupies lower address position in memory! RISC-V Registers(explored again later..) Register File Temporary registers t0…t6 Procedures(callee functions) can destroy these Saved registers s0..s11, but are caller save Procedures (callee functions) must save/restore these zero register is always 0 a0..a7 Are passed to functions as parameters a0..a1 Are returned from functions ‹#› Memory “Segments” Three segments for now Reserved: 0x0000_0000 to 0x0040_0000 Special code for I/O and OS Program Text: 0x0040_0000 to 0x1000_0000 Machine code for your instructions! Static Data 0x1001_0000 to 0x1004_0000 Data that is allocated before your program runs RISC-V Example Divisible By Four Program Sequence of 7 Instructions Run in RARS https://github.com/TheThirdOne/rars File(and also install files) provided in Google Drive->RARS sample programs ‹#› Main Memory Instructions stored in memory. The first instruction is always at 0x0040 0000 Each instruction is 32 bits long (4 Bytes, 1 byte = 8 bits) 7 instructions = 7 * 4 bytes = 28 bytes (size of the program). Instructions stored sequentially in memory with the address of the next instruction being +4 of the previous instruction ‹#› Running Program in RARS Running Program in RARS ‹#› RISC-V Instruction Encoding example All instructions exactly 32 bits wide Different formats for different purposes Similarities in formats ease implementation op rs rt offset 6 bits 5 bits 5 bits 16 bits op rs rt rd funct shamt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Format I-Format op address 6 bits 26 bits UJ-Format 31 0 31 0 31 0 Von Neumann and RISC-V RISC-V Instruction Basics R-type instructions: or a0, t2, t4 op rs, rt, rd, shift amount, funct: rd - destination, rs - source 1, rt source 2 op - 6 bits rs - 5 bits rt - 5 bits funct - 6 bits rd - 5 bits shamt - 5 bits This instruction is an example of Register Addressing ‹#› I-Type Instructions Arithmetic Immediate Example (using decimal notation): addi t1, t2, 23 t1 = t2 + 23 Can use hex notation (useful for masking): andi t1, t2, 0x000F t1 = t2 & 0x000F This instruction is an example of Immediate Addressing Logical Operations Also have sra (shift right arithmetic) and srai (shift right arithmetic immediate) ‹#› Regarding SUB instructions SUB t1, t2, t3 - Means t1 = t2 – t3 RISC-V Overview - Commands RISC-V instructions can be broken down into 3 categories: Data Movement Move data between memory and registers For example: lw is load word, sw is store word For example: ld is load doubleword, sd is store doubleword Operate Manipulate data directly For example: add is addition, xor is logical Control Change the sequence of instruction execution For example: b is branch, jal is jump and link, ret is return ‹#› Data-Movement: Load Instructions Move data from memory to a register ‹#› Register Memory Data transfer Endianness: Memory aid for exams Little Endians Big Endians Least significant byte of data occupies lower address position in memory! Most significant byte of data occupies lower address position in memory! Lol ‹#› Base addressing ld t1, 0(t2) “ load a doubleword into t1 from address pointed to by t2” t2 contains an address t1 = memory[t2] NOTE: ld t1, t2 is not valid syntax! 1210 Reg0 Reg1 Reg2 Reg3 Example: Assume four 64-bit registers, Little Endian ordering in memory 0x29 0xA5 0x01 0xFF 16 17 18 19 ld Reg1, 0(Reg2); Reg1=? 0x99 0xA5 0x54 0xFD 12 13 14 15 0x10 0xA0 0x09 0x00 8 9 10 11 Reg1= 0x FF 01 A5 29 FD 54 A5 99 Memory address Base + offset addressing ld t1, 4(t2) Instruction contains 16-bit immediate offset (4 in example) Effective address is t2+4 t1 = memory[t2+4] NOTE: ld t1, 0(t2) is the same as indirect addressing! Immediate offset is 16-bit *signed* and we can load adjacent words: ld t1, -4(t2) ld t2, 0(t2) ld t3, 4(t2) Endianness: Memory aid for exams Little Endians Big Endians Least significant byte of data occupies lower address position in memory! Most significant byte of data occupies lower address position in memory! Lol ‹#› Base addressing 1210 Reg0 Reg1 Reg2 Reg3 Example: Assume four 64-bit registers, Little Endian ordering in memory, byte addressable (always implicit if not mentioned) Problem 1: ld Reg1, 0(Reg2); Reg1=? Reg1= 0x FF 01 A5 29 FD 54 A5 99 Problem 2: ld Reg1, 4(Reg2); Reg1=? Reg1= 0x 0F 29 A0 10 FF 01 A5 29 0x29 0xA5 0x01 0xFF 16 17 18 19 0x99 0xA5 0x54 0xFD 12 13 14 15 0x10 0xA0 0x09 0x00 8 9 10 11 Memory address Problem 3: lw Reg1, -4(Reg2); Reg1=? Reg1= 0x 00 00 00 00 00 09 A0 10 0x10 0xA0 0x29 0x0F 20 21 22 23 Load data sizes DoubleWords are 64-bit