*timescale Ins / lps module mux (input I0, Il, slct, output out); wire slct n; wire out_l; wire out_2; not (slct_n, slct); and (out_1, IO, slct_n); and (out_2, Il, slct); or (out, out_1, out_2);...

Extracted text: *timescale Ins / lps module mux (input I0, Il, slct, output out); wire slct n; wire out_l; wire out_2; not (slct_n, slct); and (out_1, IO, slct_n); and (out_2, Il, slct); or (out, out_1, out_2); endmodule 'timescale Ins / lps module testbench (); reg 10, I1, slct; wire out; integer i; mux dt (.10 (I0), .Il (Il), .slct (slct), .out (out)); initial begin 10=0; Il=0; slct=0; Smonitor ("slct=%0b 10=$0b Il=%0b out=30b",slct,I0, I1, out); for (i=0; i<8; i="i+l)begin" {slct,="" 10,="" i1}="i;" #10;="" end="" end="" initial="" #80="" $finish;="" endmodule="" which="" of="" the="" following="" is="" true="" for="" the="" above="" 2="" verilog="" codes?="" i.="" gate="" design="" level="" is="" used="" in="" the="" code.="" ii.="" 2x1="" multiplexer="" is="" designed="" in="" the="" code.="" ii.="" all="" nets="" in="" the="" codes="" must="" be="" defined="" in="" the="" "testbench"="">