Tree-based buses. Show how the logical bus using point-to-point links of Figure 22.16 can be realized with lower delay by arranging both the OR network and the repeater chain into trees. Assume that this bus is being placed on a 12mm square chip, each module is 2mm square, and a repeater or logic gate must be placed each 2mm along a line to maintain signaling speed. Further assume that a signal takes one unit of time to traverse 2mm of wire and one gate. Compare the maximum latency of this 36-module system with linear OR and repeater networks and tree-structured OR and repeater networks.
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