Write a VHDL structural model design (using the model listed below) for a simple 4-bit recirculating shift-Register.For simplicity the model has only one control input which goes into an XOR gate in...

Write a VHDL structural model design (using the model listed below) for a simple 4-bit recirculating shift-Register.For simplicity the model has only one control input which goes into an XOR gate in front of D-input of the first flip flop. That signal called ExternalData_h input allows forcing 1's or 0's into that flip flop D-input. The other input of the XOR is recirculating Q-output from the fourth flip flop into that first flip flop. Below you are given the interface for the model of the D-type flip flop, which you are going to use (together with the expression using the XOR operator) to create the structural model for the recirculating 4-bit shift register (using 44 FF instances). A.Write the Entity Declaration B.Declare components and wiring signals within the Architecture C.Write the Architecture Begin-End block showing the interconnection D.between the flip-flops Entity Declaration for the Flip Flop Model Entity DFF is Prt(0, Clk, Cir: in std_logic; Q: out std_logic); End DFF;