1. Design a computational unit that can do the following operations: Add, subtract, multiply, and, or, xor, nand, pass. Inputs and outputs are 8-bit long. Design two rows of ALUs and connect the two...

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1. Design a computational unit that can do the following operations: Add, subtract, multiply, and, or, xor, nand, pass. Inputs and outputs are 8-bit long. Design two rows of ALUs and connect the two rows using the connectivity 5:1, 3:1, 5:1, 3:1, 5:1 as shown in the figure below. Design it using structural VHDL and submit the source code, test bench, RTL schematics, simulation waveforms with report containing some of the test cases and their explanation. The codes must be properly commented. 2. Use the same ALU designed in Q1, design a hierarchical reconfigurable architecture as explained in the class and show in the figure below. Each processing cell can have either one ALU / CU or a group of ALUs / CUs. The ALUs /CUs within a cell are programmed to do specific operations shown in the hand drawn figure. Inputs and outputs are 8-bit long. The outputs of all processing cells will be stored in an output register file. Design it using structural VHDL and synthesize it. Submit the source code, test bench, RTL schematics, simulation waveforms with report containing some of the test cases and their explanation. The codes must be properly commented. USE VIVADO SOFTWARE 2018.3 VERSION. ONLY USE VHDL STYLE MY TEACHER DOESN’T ACCEPT ANYTHING ELSE. PLEASE FULLY DO BOTH PROGRAMS EXACTLY HOW THE QUESTIONS AND PICTURES DEPICT. INCLUDE BOTH TEST BENCH FILES AND MAKE SURE THE RESULTS THEY OUTPUT ARE EASILY UNDERSTANDABLE BY MY INSTRUCTOR. PLEASE INCLUDE 5 jpg PICTURES OF THE TEST CASES FOR PROBLEM 1 AND ALSO FOR PROBLEM 2.