[20] Question 1–Superscalar and Multicore Conceptsa) Explain the difference between the type of parallel execution that multiple cores allows and the type of parallel execution that a superscalar architectureallows.b) On a system with many different programs actively running simultaneously, which CPU feature is preferable for overall performance benefit –multi-core or superscalar architecture?Explain why.c) On a system with very few (usually 1)different programs actively running simultaneously, which CPU feature is preferable for overall performance benefit –multi-core or superscalar architecture?Explainwhy.[20] Question 2-Data DependenciesIdentify all the data dependencies inthe codeon the right. For each dependency, identify if it is a read-write dependency, a write-readdependency, or a write-write dependency. NOTE: identify all data dependencies, even if you don’t expect them to cause delays. You may express the dependencies as either a drawn graph(labelling the arrows with the type of dependency), or as a list of dependenciesof the format:statement1 -> statement2 [type]where statement1 is the identifierof one statement, and statement2 is the identifier of a statement thatcan’t happen until after statement1. Type should be one of:•“read-write”,meaningthe value in the register can’t be read by one statement until a previous statement has written its value.•“write-read”,meaningthe value in the register can’t be writtenby one statement until aprevious statement has readits value.•“write-write”,meaningthe value in the register can’t be writtenby one statement until a previous statement has written its valuefirst.[20] Question 3–Reordering for SuperpipeliningWhat is an optimal reordering of the statements in question 2 for a 2-way superscalar, pipelined processor? How many clock cycles does it take to execute the instructions?Assume both functionalunits allow both arithmetic and load/store instructions. IDStatementAMOV r1, #5BADDr2, r1, #10CMOV r3, #3DMUL r4, r1, r1EMOV [r0], r4FMOV r5, #8GADD r6, r3, r5HMOV r5, #6[20] Question 4–SuperscalarPerformanceAssume we are designing a superscalar processor, with 3 different possible types of Functional Units: Load/Store, Integer, and FloatingPoint Units. For this question, assume that we can not make one functionalunit that does multiple different types of operations. We are given the following table of frequency that the processor is asked to execute the different types of instructions:TypeFrequencyInteger49%Floating Point8%Load/Store43%a)If we produce a 3-way superscalar architecture, which functionalunits should we include?b)If we produce a 4-way superscalar architecture, which functionalunits should we include?c)If we produce a 5-way superscalar architecture, which functionalunits should we include?[20] Question 5–Register File ImpactsIn a superscalar processor, each core has 1 register file. Thus, inside a given core, the functional units all access the same register file simultaneously.Write the Verilog code for a register file module that could be used with a 2-way superscalar processor. Make sure that if both functional units try to write to the same register file at the same time, only the second one willtake effect.Note:•You may start with code from the project and modify it.•Consider how many read ports and how many write ports are needed.Bonus [up to 3pts on term, depending on the thoroughness and accuracyof the description]There is a technique called “loop unrolling”whichcompilersuseto optimize code performance. Explain what loop unrolling is, and how itinteracts with pipeline and superscalar featuresin a processor toimprovecode performance. Use this loop as an examplethroughoutyour description:for (i = 0; i b[i] = 5 * a[i];}