[email protected]EEE 312 ELECTRONICS II – Spring 2020 Homework 2 – Due on March 13th in Class (out of 100 pts.) Use the following parameter values unless specified otherwise in the question: VBE(SAT)=0.8 V, VCE(SAT)=0.15 V, VBE(FA)= VBC(RA)= VBE(ECL)=0.7 V, βF=100, βR=0.06, σO=0.8. Use VD(ON)=0.7 V for any diode. 1. (8 pts.) For the RTL inverter with active pull-up in the given figure, use VCC=5 V, βF=100, VBE(FA)=0.7 V, VBE(SAT)=0.8 V, VCE(SAT) =0.16 V for all BJTs. Find IBP, ICP, and VOUT for: a) (4 pts.) VIN=0 V, N=0 (no load) b) (4 pts.) VIN=0 V, N=3 VIN RBP VCC VOUT=VIN’ QP RCPRC QS RBS RBO QO 1.5kΩ 100Ω 3.6kΩ 1.5kΩ 1.5kΩ N Identical gates 2. (14 pts.) Given the following circuit: 5 k Y 10 k C 5 k A B 2.5 k 3 k D1 D2 Q1 Q2 Q3 D3 5 V i. (2 pts.) What is the logic function? ii. (12 pts.) What are the values of input DC voltage specs (VIL/VIH) for each of the inputs A, B, and C? 3. (32 pts.) Given the following digital circuit: 1 k 2 k 5 V 4 k Q3 Q4 Q5 Q6 Q1 Y A B 1.6 k Q2 D1 D2 a) (2 pts.) What is the implemented logic function, Y (provide a Boolean equation)? b) (4 pts.) Which region of operation is Q3 in, when the output Y is ‘low’ (VL)? Provide a justification. c) (4 pts.) Does the diode D1 ever enter CUTOFF? If yes, for which values of A and B? d) (12 pts.) Derive all critical DC voltage points for the circuit, and sketch the VTC. e) (10 pts.) What is the power dissipation of this circuit (output not loaded)? 4. (32 pts.) The following figure depicts a driving gate and a load. The light emitting diode (LED) in the load have VF=2 V. The load is connected to the driving gate only in sections (e) and (f) of this question. VBE(SAT)=0.8 V, VCE(SAT)=0.15 V, VBE(FA)= VBC(RA)= VBE(ECL)=0.7 V, βF=100, βR=0.06, σO=0.8. 5 V Q1 Q2 5 k 3 k 1k A B Q4 200 Q5 Q6 Y 5 V 2.5 k IN a) (2 pts.) What is the implemented logic function, Y (provide a Boolean equation)? b) i. (2 pts.) Which region of op- eration is Q4 in, when the output Y of the driving gate is ‘low’ (VOL)? Provide an analytical justification. ii. (2 pts.) Is there a “breakpoint” in the VTC of the given driving gate? Explain for full credit. c) (10 pts.) Derive an estimation of all critical DC voltage points for the driving gate, and sketch the VTC. You may assume inputs A and B are tied together for this part. d) (8 pts.) What is the total power dissipation of the driving gate and the load circuit together, when the gate output Y is connected to the load input IN? Clarify any assumptions you make. e) (8 pts.) Calculate, and recommend the maximum number of LED loads, similar to the one shown in the previous page, that could be connected to the driving gate (fanout limit). 5. (14 pts.) The following digital circuit has an empirically characterized VIH-VIL window of ~0.1 V, and vREF = 1 V at all times. Complete the design of the circuit by deriving suitable values for R1, R2, and R3, if the circuit is to have 0.5 V symmetric noise margin, and 5 mW power dissipation. Clarify any assumptions in your derivation. VBE(SAT)=0.8 V, VCE(SAT)=0.15 V, VBE(FA)= VBC(RA)= VBE(ECL)=0.7 V, βF=100, βR=0.06, σO=0.8. -1 V R1 vI vREFvO1 1 mA Q3 Q1 Q2 Q4 3.3 V 1.5 kΩ R2 R2 1.5 kΩ R3 R3 LED Load