Assignment NIT3104 12h/24h Digital Clock Circuit Design Using 7493 The 4 blocks of a digital clock are  1 Hz clock generator to generate 1 PPS (pulse per second) signal to the seconds block. ...

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Assignment NIT3104 12h/24h Digital Clock Circuit Design Using 7493 The 4 blocks of a digital clock are  1 Hz clock generator to generate 1 PPS (pulse per second) signal to the seconds block.  SECONDS block - contains a divide by 10 circuit followed by a divide by 6 circuit. Will generate a 1 PPM (pulse per minute) signal to the minutes block. The BCD outputs connect to the BCD to Seven Segment circuit to display the seconds values.  MINUTES block - identical to the seconds block it contains 2 dividers; a divide by 10 followed by a divide by 6. Will generate a 1 PPH (pulse per hour) signal to the HOURS block. The BCD outputs connects to the BCD to Seven Segment circuit to display the minutes values.  HOURS block - depending on whether it is a 12 or 24H clock, will have a divide 24 or divide by 12. For 24H, it will count from 00 to 23. For 12H, it will count from 00 to 11. The BCD outputs connects to the BCD to Seven Segment circuit to display the hours values. SECONDS block The 74LS93 is used to implement the divide by 10 and divide by 6 circuits. The 74LS93 is a high- speed 4-bit ripple type counters partitioned into two sections. The counter has a divide-by-two section and divide-by-eight section which are triggered by a HIGH-to-LOW transition on the clock inputs. Please go to truncated ripple counter to learn how the 74LS93 works. Divide by 10 Counter http://electronics-course.com/number-systems http://electronics-course.com/bcd-7-segment http://electronics-course.com/truncated-ripple-counter  In order to use all 4 bits of the counter, Q0 must be connected to CP1. Q0 is LSB and Q3 is MSB.  The input clock is connected to CP0.  To implement a divide by 10 or MOD10 counter, Q1 is connected to MR1 and Q3 is connected to MR2. With this connection, when the count reaches 10 (1010 binary), it resets to 0.  The output frequency at Q3 is the input clock frequency divided by 10.  To display the values, Q3..Q0 are connected to the respective D..A inputs of the BCD to 7 segment display. Divide by 6 Counter  Since only 3 bits are required Q0 is not used. Q1 is LSB and Q3 is MSB.  The input clock is connected to CP1.  To implement a divide by 6 or MOD6 counter, Q2 is connected to MR1 and Q3 is connected to MR2. With this connection, when the count reaches 6 (110 binary), it resets to 0.  The output frequency at Q3 is the input clock frequency divided by 6.  To display the values, Q3..Q1 are connected to the respective C..A inputs of the BCD to 7 segment display. D of the BCD to 7 segment display input is connected to GND. HOURS block The clock can be designed as a 24H or 12H clock. We will explain the steps to arrive at the combinational logic to obtain a 12H clock and we will leave it to the reader to design the 24H clock as an exercise. Click hints if you need help to design the 24H clock. 12H Clock  In order to use all 4 bits of the IC1 (ones) counter, Q0 must be connected to CP1. Q0 is LSB and Q3 is MSB. The input clock is connected to CP0.  Since less than 3 bits are required for IC2 (tens), Q0 is not used. Q1 is LSB and Q3 is MSB. The input clock is connected to CP1.  The truth table of the counter is abbreviated - omitting those rows where the MR inputs to the counters are 0. Recall that for the 7493, a 1 to the MR will reset the counters to 0.  To simplify the table, K is Q0 of IC1 (ones), G is Q0 of IC2 (tens) and so on.  For the 12H clock, when the count in BCD reaches o 0A, IC1 must be cleared (Y=1) http://electronics-course.com/digital-clock#hide o 12, IC1 must be cleared (Y=1) and IC2 must be cleared (X=1)  Using SOP (sum of products), we obtain o Y = HJ + GJ where Y is the IC1 MR1, MR2 inputs connected together o X = GJ where X is the IC2 MR1, MR2 inputs connected together Simulate and Breadboard the 24H Clock circuit. 1 Hz Clock The 1 Hz clock can be implemented using the schmitt trigger oscillator. Limitations  The clock cannot be set to the correct time. Hint - use additional logic to allow the 1 PPS clock to drive the MINUTES and HOURS block depending on a button press. Below is the block diagram of one solution using a 2 to 1 multiplexer. Depending on SET, either the 1 PPS (Pulse Per Second) or the 1 PPH (Pulse Per Hour) clock drives the Hour circuit.  The 12H clock counts from 00 to 11 rather than 01 to 12. Hint - use regular JK flip flops (74LS73) instead of the 74LS93 so on terminal count, the counter output is preset to 01. http://electronics-course.com/sum-of-products http://breadboard.electronics-course.com/24h-clock http://electronics-course.com/schmitt-trigger-oscillator http://electronics-course.com/mux#tt2
Answered Same DaySep 20, 2020

Answer To: Assignment NIT3104 12h/24h Digital Clock Circuit Design Using 7493 The 4 blocks of a digital clock...

Gaurav answered on Sep 24 2020
137 Votes

0

-11.2493,7.22722,159.995,-88.1382

2
BB_CLOCK
-0.5,-16.5

CLK1

angle 0.0
HALF_CYCLE 25


16
EE_VDD
22.5,-6.5

OUT_025

angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1


30
BA_NAND2
43,-25.5

IN_02

IN_112

OUT16

angle 180
INPUT_BITS 2gate>

46
DE_TO
9.5,-16.5

IN_01
angle 0.0
JUNCTION_ID clk


50
DE_TO
32,-12

IN_029
angle 90
JUNCTION_ID q0


52
DE_TO
46.5,-12

IN_012
angle 90
JUNCTION_ID q1


54
DE_TO
56,-12

IN_028
angle 90
JUNCTION_ID q2


56
DE_TO
69.5,-12

IN_02
angle 90
JUNCTION_ID q3


60
DE_TO
34,-23

IN_029
angle 0.0
JUNCTION_ID q0'


64
BE_JKFF_LOW_NT
39.5,-16.5

J25

K25

Q12


clear16

clock29
angle 0.0
SYNC_CLEAR false
SYNC_SET false


66
BE_JKFF_LOW_NT
52,-16.5

J25

K25

Q28


clear16

clock12
angle 0.0
SYNC_CLEAR false
SYNC_SET false


68
BE_JKFF_LOW_NT
64,-16.5

J25

K25

Q2


clear16

clock28
angle 0.0
SYNC_CLEAR false
SYNC_SET false


70
BE_JKFF_LOW_NT
27.5,-16.5

J25

K25

Q29


clear16

clock26
angle 0.0
SYNC_CLEAR false
SYNC_SET false


74
DA_FROM
17,-16.5

IN_026
angle 0.0
JUNCTION_ID clk


80
GE_LED_DISPLAY_4BIT
99.5,-56

IN_030

IN_131

IN_232

IN_333
VALUE_BOX -1.9,-2.9,1.9,3.9
angle 0.0
CURRENT_VALUE 4
INPUT_BITS 4
NO_HOLD true
SYNC_LOAD false
UNKNOWN_OUTPUTS false


82
DA_FROM
91,-41.5

IN_033
angle 0.0
JUNCTION_ID q3


83
DA_FROM
91,-44

IN_032
angle 0.0
JUNCTION_ID q2


84
DA_FROM
91,-46.5

IN_031
angle 0.0
JUNCTION_ID q1


85
DA_FROM
91,-49

IN_030
angle 0.0
JUNCTION_ID q0'


86
GE_LED_DISPLAY_4BIT
87.5,-56.5

IN_040

IN_141

IN_242

IN_343
VALUE_BOX -1.9,-2.9,1.9,3.9
angle 0.0
CURRENT_VALUE 3
INPUT_BITS 4
NO_HOLD true
SYNC_LOAD false
UNKNOWN_OUTPUTS false


88
BE_JKFF_LOW_NT
28.5,-40.5

J36

K36

Q34


clear38

clock39
angle 0.0
SYNC_CLEAR false
SYNC_SET false


90
BE_JKFF_LOW_NT
40,-40.5

J36

K36

Q35


clear38

clock34
angle 0.0
SYNC_CLEAR false
SYNC_SET false


92
BE_JKFF_LOW_NT
52.5,-40.5

J36

K36

Q3


clear38

clock35
angle 0.0
SYNC_CLEAR false
SYNC_SET false


94
EE_VDD
22,-31.5

OUT_036

angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1


96
BA_NAND2
42,-51

IN_03

IN_135

OUT38

angle 180
INPUT_BITS 2


98
DA_FROM
19.5,-40.5

IN_039
angle 0.0
JUNCTION_ID 10sec


100
DE_TO
38,-28

IN_016
angle 180
JUNCTION_ID 10sec


102
DE_TO
57,-35.5

IN_03
angle 90
JUNCTION_ID Q3


103
DE_TO
44,-36

IN_035
angle 90
JUNCTION_ID Q2


104
DE_TO
32,-36

IN_034
angle 90
JUNCTION_ID...
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