Please help me with this assignment, thanks
EE 201A – Project Description Prof. Puneet Gupta page 1/8 UCLA EE 201A -- VLSI Design Automation -- Winter 2018 Course Project: Automated Inter-Chip Pin Assignment TA: Saptadeep Pal and Wei-Che Wang ***** IMPORTANT ***** • Run your experiments and do your work on SEASnet server eeapps.seas.ucla.edu • You will work in teams of two students. The project has a competitive grading component. o How you coordinate your work is up to you. We recommend a version control system like Git. o Be careful not to reveal your project directory to other teams! • All your work should be done in /w/class.2/ee/ee201a/YOUR_SEASNET_USERNAME/ o Don’t do the project in your SEASnet home directory (~). o You are responsible for backing up your code & data. • You can get the latest version of the materials at /w/class.2/ee/ee201a/ee201ota/material/project/ o Subject to updates over the quarter, but will be uploaded as separate tarballs (v1, v2, etc). • Due Dates: o 1) Final Code Submission – Monday, March 12, 2018 @ 10:00:00 PM PT o 2) Presentations w/TA-Verified Results – Thursday, March 15, 2018 (in class) • Start early! This project will be challenging. There are also expected license and server load issues from this as well as other courses in the last few weeks. You should try and get most work done before that. • See the end for important submission instructions. Project Overview Routing at the global chip/system level connecting pins of various design blocks, soft/hard IP blocks or macros is often a critical part of the physical design flow. Due to the size and complexity of the design, each block or module is often individually processed to create a layout, and then combined with other macros in the system floorplan. However this approach leaves the pin assignment inside the block agnostic of the global net connectivity. This has adverse effects on performance, timing/skew matching as well as overall system area. Your job is to research and develop a prototype pin assignment tool in C++ with the OpenAccess API. The input floorplan would have hard macro blocks (that can be treated as black-boxes for our purpose) with an initial default pin placement. Your tool would then need to allocate improved pin locations along the block peripheries to minimize routing wirelength, subject to various constraints described in later sections. Your overall goal should be to learn how to approach open-ended electronic design problems through an automated solution. Ideally, you would produce a robust and useful tool that could be leveraged by others. This means the tool should not be designed to just barely satisfy the project requirements. Your approach should take a broader scope by incorporating relevant ideas from research literature. You would also need to budget time sufficient for an iterative design process, since the complete flow includes testing on a commercial P&R tool with significant runtimes due to design complexity. EE 201A – Project Description Prof. Puneet Gupta page 2/8 Your final solution should be well designed, implemented, and documented. The project also includes a presentation that is a significant component of your grade. For a good grade, make sure you leave enough time to do this well! All of these skills are essential to working in industry. The project may appear very daunting at first glance. However, as you familiarize yourself with the tool and assignment, it will get easier. Don’t get discouraged if you are having difficulty meeting the design objectives – other students are likely also struggling! For this reason, you are not graded on an absolute points basis. Do your best! Notes: • Read and understand the provided material including source code, scripts, testcases, constraints, and design flow as soon as possible. • You will find it useful to refer to the OA tutorial from class and the official OA documentation. • It is recommended that you adopt version control such as Git for collaborating with your teammate. If you are not comfortable with Git, you can read Mark’s tutorial at https://markgottscho.wordpress.com/2015/01/24/a-brief-git- tutorial-for-collaborative-research/ . We also recommend beginners start with www.gitimmersion.com . • Please use Piazza for asking (and answering) questions before coming to office hours. • Since you are expected to work on the assignment in teams of two, do not provide solutions or compare results with other teams. Design Objectives The Pin Assignment tool should accomplish the following: • For each type of macro/block in a given testcase, determine a pin assignment solution such that the inter- macro wirelength is minimized. This is hierarchical pin placement since all instances of a particular macro should have identical pin assignment. • You are allowed to add at most one extra physical copy of a pin around the periphery of the macro. This is multi-pin placement. Since hard macros are often integrated on passive substrates, once the signal leaves the macro boundary, there is no opportunity of buffering the signals. In case, only one pin location is allowed, some nets might be too long, and this would result in the signals dying down before they reach the destination macro. Multi-pin strategy allows such nets to be internally routed and buffered through the source macro and the nets would exit through the nearest-to-the destination pin locations. o Ensure that you maintain hierarchical pin placement strategy, i.e., the pin assignment for the instances of a macro should be same. You will finally notice that, top-level P&R would choose the best copy of the pin and in that case, different instances of a macro would have nets connected to https://markgottscho.wordpress.com/2015/01/24/a-brief-git-tutorial-for-collaborative-research/ https://markgottscho.wordpress.com/2015/01/24/a-brief-git-tutorial-for-collaborative-research/ http://www.gitimmersion.com/ EE 201A – Project Description Prof. Puneet Gupta page 3/8 different copies of the same logical pin. You need not worry about that. The goal should be to ensure that all the instances of a macro get same physical locations of each pin before P&R. • In case there is a constraint on maximum perturbation, for every pin, the Manhattan distance between the new and the old location must be within the amount of perturbation allowed. In case there are two copies of the pin, the total (or mean) perturbation should be minimized. For example, if a pin’s original location is (x1, y1) and new location of two copies are (x11, y11) and (x12, y12), the total perturbation would be (|x11 -x1|+ |x12-x1|+|y11 -y1|+ |y12-y1|). • The initial placement of the macros shouldn’t be perturbed. However, you are allowed to rotate the macros without changing the location of the center of the macro. Note that, mirroring the block is not allowed. These are the specific objectives for your Pin Assignment tool: • Your tool should be robust in order to meet different sets of input rules across various test cases. • The primary objective is to minimize wirelength after routing from Innovus based on your improved pin assignment. This means that your algorithm would need an effective routing/congestion prediction mechanism to evaluate different pin locations based on connectivity. • You should minimize both maximum and mean net wirelength for improved performance. • The macro pin placement must honor a specified minimum pitch (inter-pin distance). Pins must also be moved in discrete steps of the metal track spacing for the pin metal layer, as opposed to a continuous movement along the macro periphery. This will ensure DRC compliance. The initial input pin assignment will honor the defined minimum pitch. • You can assume that all pins on all macros for a specific design will be on the same metal layer and thus have the same metal track spacing, specified in the input rules. • Your algorithm should minimize total perturbation of pins from their default locations, since a standard flow would require an additional step to fix internal layouts of the sub-blocks if their pins have been externally moved. • Your algorithm should also add extra copies of a pin only if required since additional copies would mean additional internal routing and power consumption. Try to minimize the number of additional pin copies. • In the provided macros, you cannot touch internal layouts other than to alter pin locations. The system-level routing will use specific higher metal layers using an automated Innovus routine, whereas the macros will have internal routing in lower layers. You cannot move system pins at the top-level design boundary. • The final routing result must meet basic layout versus schematic (LVS) and design rule checks (DRC) within Innovus. This means that your tool must not alter original connectivity, delete/rename essential pins, make pins inaccessible, place pins too close together to be routable, and so on. • Your algorithm/heuristic should be well designed to have efficient runtime. Multiple iterations are permitted through the Innovus flow (maximum of 5) for an improved result, but this will have a hit on runtime. Flow Inputs This section describes some important inputs to the Pin Assignment tool-flow. You will be provided with some starter material and directory structure according to these specifications to help get started. The entire tool-flow will be automated using a push-button script relying on this directory and filename structure. Ensure that your tool works correctly in this exact flow – otherwise, your project cannot be graded. The major inputs to the flow are described in Table 1 below: EE 201A – Project Description Prof. Puneet Gupta page 4/8 Table 1. Input file type descriptions. File Type Description System design DEF Contains global floorplan, placed macros, placed system pins, and net connectivity (unrouted). No changes can be made here. Block macro LEFs Individual files for each unique macro used in the system. Contain entire physical layout information. Only editing pin locations is permitted. Technology LEF (Nangate 45nm) Describes physical information for various metal and via layers, and basic design rules such as metal track pitch and minimum same-net spacing. Testcase-specific input rules Described below. Innovus Tcl Script Used for an automated Innovus flow after improved pin assignment for complete routing, LVS/DRC checks, reports