subtract_5Byte/ASM_layout.hwl
OPEN source 0 0 60 42
Source < attributes TOOLTIP on,TOOLTIP_FORMAT signed,TOOLTIP_MODE details,FREEZE off,MARKS off
OPEN assembly 60 0 40 30
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,FORMAT Auto,FREEZE off,TOPPC 0x400A
OPEN procedure 60 60 40 17
Procedure < attributes VALUES on,TYPES off
OPEN register 60 30 40 30
Register < attributes FORMAT AUTO,COMPLEMENT None
OPEN memory 60 77 40 23
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,MODE automatic,UPDATERATE 10,ADDRESS 0x80
OPEN data 0 42 60 28
Data < attributes SCOPE global,COMPLEMENT None,FORMAT Hex,MODE automatic,SORT NotSort,UPDATERATE 10,NAMEWIDTH 16
OPEN command 0 70 60 30
Command < attributes CACHESIZE 1000
bckcolor 50331647
font 'Courier New' 9 BLACK
AUTOSIZE on
ACTIVATE "Assembly" "Memory" "Register" "Command" "Procedure" "Data" "Source"
subtract_5Byte/bin/main.dbg
;*****************************************************************
;* This stationery serves as the framework for a *
;* user application (single file, absolute assembly application) *
;* For a more comprehensive program that *
;* demonstrates the more advanced functionality of this *
;* processor, please see the demonstration applications *
;* located in the examples subdirectory of the *
;* Freescale CodeWarrior for the HC12 Program directory *
;*****************************************************************
; export symbols
XDEF Entry, _Startup ; export 'Entry' symbol
ABSENTRY Entry ; for absolute assembly: mark this as application entry point
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
; Note: This file is recreated by the project wizard whenever the MCU is
; changed and should not be edited by hand
;
; include derivative specific macros
INCLUDE 'MC9S12C128.inc'
; Based on CPU DB MC9S12C32_80, version 2.87.408 (RegistersPrg V2.28)
; ###################################################################
; Filename : mc9s12c128.inc
; Processor : MC9S12C128CFU16
; FileFormat: V2.28
; DataSheet : MC9S12C128 Rev 01.23 05/2007
; Compiler : CodeWarrior compiler
; Date/Time : 2.7.2009, 8:35
; Abstract :
; This header implements the mapping of I/O devices.
;
; Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
;
; http : www.freescale.com
; mail : [email protected]
;
; CPU Registers Revisions:
; - 08.12.2006, V2.87.396:
; - Added bit CRGFLG_LVRF. REASON: Bug-fix (#4020 in Issue Manager)
;
; File-Format-Revisions:
; - 14.11.2005, V2.00 :
; - Deprecated symbols added for backward compatibility (section at the end of this file)
; - 15.11.2005, V2.01 :
; - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family.
; - 17.12.2005, V2.02 :
; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
; - 16.01.2006, V2.03 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
; - 08.03.2006, V2.04 :
; - Support for bit(s) names duplicated with any register name in .h header files
; - 24.03.2006, V2.05 :
; - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order.
; - 26.04.2006, V2.06 :
; - Changes have not affected this file (because they are related to another family)
; - 27.04.2006, V2.07 :
; - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
; - 07.06.2006, V2.08 :
; - Changes have not affected this file (because they are related to another family)
; - 03.07.2006, V2.09 :
; - Changes have not affected this file (because they are related to another family)
; - 27.10.2006, V2.10 :
; - __RESET_WATCHDOG improved formating and re-definition
; - 23.11.2006, V2.11 :
; - Changes have not affected this file (because they are related to another family)
; - 22.01.2007, V2.12 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #4086.
; - 01.03.2007, V2.13 :
; - Flash commands constants values converted to HEX format
; - 02.03.2007, V2.14 :
; - Interrupt vector numbers added into .H, see VectorNumber_*
; - 26.03.2007, V2.15 :
; - Changes have not affected this file (because they are related to another family)
; - 10.05.2007, V2.16 :
; - Changes have not affected this file (because they are related to another family)
; - 05.06.2007, V2.17 :
; - Changes have not affected this file (because they are related to another family)
; - 19.07.2007, V2.18 :
; - Improved number of blanked lines inside register structures
; - 06.08.2007, V2.19 :
; - CPUDB revisions generated ahead of the file-format revisions.
; - 11.09.2007, V2.20 :
; - Added comment about initialization of unbonded pins.
; - 02.01.2008, V2.21 :
; - Changes have not affected this file (because they are related to another family)
; - 13.02.2008, V2.22 :
; - Changes have not affected this file (because they are related to another family)
; - 20.02.2008, V2.23 :
; - Termination of pragma V30toV31Compatible added, #5708
; - 03.07.2008, V2.24 :
; - Added support for bits with name starting with number (like "1HZ")
; - 28.11.2008, V2.25 :
; - StandBy RAM array declaration for ANSI-C added
; - 1.12.2008, V2.26 :
; - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
; - 17.3.2009, V2.27 :
; - Merged bit-group is not generated, if the name matches with another bit name in the register
; - 6.4.2009, V2.28 :
; - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
;
; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
; derivative device. To avoid extra current drain from floating input pins, the user’s reset
; initialization routine in the application program must either enable on-chip pull-up devices
; or change the direction of unconnected pins to outputs so the pins do not float.
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
RAMStart: equ $00000400
RAMEnd: equ $00000FFF
ROM_4000Start: equ $00004000
ROM_4000End: equ $00007FFF
ROM_C000Start: equ $0000C000
ROM_C000End: equ $0000FEFF
PAGE_38Start: equ $00388000
PAGE_38End: equ $0038BFFF
PAGE_39Start: equ $00398000
PAGE_39End: equ $0039BFFF
PAGE_3AStart: equ $003A8000
PAGE_3AEnd: equ $003ABFFF
PAGE_3BStart: equ $003B8000
PAGE_3BEnd: equ $003BBFFF
PAGE_3CStart: equ $003C8000
PAGE_3CEnd: equ $003CBFFF
PAGE_3DStart: equ $003D8000
PAGE_3DEnd: equ $003DBFFF
;
VReserved63: equ $0000FF80
VReserved62: equ $0000FF82
VReserved61: equ $0000FF84
VReserved60: equ $0000FF86
VReserved59: equ $0000FF88
Vvreglvi: equ $0000FF8A
Vpwmesdn: equ $0000FF8C
Vportp: equ $0000FF8E
VReserved55: equ $0000FF90
VReserved54: equ $0000FF92
VReserved53: equ $0000FF94
VReserved52: equ $0000FF96
VReserved51: equ $0000FF98
VReserved50: equ $0000FF9A
VReserved49: equ $0000FF9C
VReserved48: equ $0000FF9E
VReserved47: equ $0000FFA0
VReserved46: equ $0000FFA2
VReserved45: equ $0000FFA4
VReserved44: equ $0000FFA6
VReserved43: equ $0000FFA8
VReserved42: equ $0000FFAA
VReserved41: equ $0000FFAC
VReserved40: equ $0000FFAE
Vcantx: equ $0000FFB0
Vcanrx: equ $0000FFB2
Vcanerr: equ $0000FFB4
Vcanwkup: equ $0000FFB6
Vflash: equ $0000FFB8
VReserved34: equ $0000FFBA
VReserved33: equ $0000FFBC
VReserved32: equ $0000FFBE
VReserved31: equ $0000FFC0
VReserved30: equ $0000FFC2
Vcrgscm: equ $0000FFC4
Vcrgplllck: equ $0000FFC6
VReserved27: equ $0000FFC8
VReserved26: equ $0000FFCA
VReserved25: equ $0000FFCC
Vportj: equ $0000FFCE
VReserved23: equ $0000FFD0
Vatd0: equ $0000FFD2
VReserved21: equ $0000FFD4
Vsci: equ $0000FFD6
Vspi: equ $0000FFD8
Vtimpaie: equ $0000FFDA
Vtimpaovf: equ $0000FFDC
Vtimovf: equ $0000FFDE
Vtimch7: equ $0000FFE0
Vtimch6: equ $0000FFE2
Vtimch5: equ $0000FFE4
Vtimch4: equ $0000FFE6
Vtimch3: equ $0000FFE8
Vtimch2: equ $0000FFEA
Vtimch1: equ $0000FFEC
Vtimch0: equ $0000FFEE
Vrti: equ $0000FFF0
Virq: equ $0000FFF2
Vxirq: equ $0000FFF4
Vswi: equ $0000FFF6
Vtrap: equ $0000FFF8
Vcop: equ $0000FFFA
Vclkmon: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PORTAB - Port AB Register; 0x00000000 ***
PORTAB: equ $00000000 ;*** PORTAB - Port AB Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTAB_BIT0: equ 0 ; Port AB Bit 0
PORTAB_BIT1: equ 1 ; Port AB Bit 1
PORTAB_BIT2: equ 2 ; Port AB Bit 2
PORTAB_BIT3: equ 3 ; Port AB Bit 3
PORTAB_BIT4: equ 4 ; Port AB Bit 4
PORTAB_BIT5: equ 5 ; Port AB Bit 5
PORTAB_BIT6: equ 6 ; Port AB Bit 6
PORTAB_BIT7: equ 7 ; Port AB Bit 7
PORTAB_BIT8: equ 8 ; Port AB Bit 8
PORTAB_BIT9: equ 9 ; Port AB Bit 9
PORTAB_BIT10: equ 10 ; Port AB Bit 10
PORTAB_BIT11: equ 11 ; Port AB Bit 11
PORTAB_BIT12: equ 12 ; Port AB Bit 12
PORTAB_BIT13: equ 13 ; Port AB Bit 13
PORTAB_BIT14: equ 14 ; Port AB Bit 14
PORTAB_BIT15: equ 15 ; Port AB Bit 15
; bit position masks
mPORTAB_BIT0: equ %00000001
mPORTAB_BIT1: equ %00000010
mPORTAB_BIT2: equ %00000100
mPORTAB_BIT3: equ %00001000
mPORTAB_BIT4: equ %00010000
mPORTAB_BIT5: equ %00100000
mPORTAB_BIT6: equ %01000000
mPORTAB_BIT7: equ %10000000
mPORTAB_BIT8: equ %100000000
mPORTAB_BIT9: equ %1000000000
mPORTAB_BIT10: equ %10000000000
mPORTAB_BIT11: equ %100000000000
mPORTAB_BIT12: equ %1000000000000
mPORTAB_BIT13: equ %10000000000000
mPORTAB_BIT14: equ %100000000000000
mPORTAB_BIT15: equ %1000000000000000
;*** PORTA - Port A Register; 0x00000000 ***
PORTA: equ $00000000 ;*** PORTA - Port A Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTA_BIT0: equ 0 ; Port A Bit 0
PORTA_BIT1: equ 1 ; Port A Bit 1
PORTA_BIT2: equ 2 ; Port A Bit 2
PORTA_BIT3: equ 3 ; Port A Bit 3
PORTA_BIT4: equ 4 ; Port A Bit 4
PORTA_BIT5: equ 5 ; Port A Bit 5
PORTA_BIT6: equ 6 ; Port A Bit 6
PORTA_BIT7: equ 7 ; Port A Bit 7
; bit position masks
mPORTA_BIT0: equ %00000001
mPORTA_BIT1: equ %00000010
mPORTA_BIT2: equ %00000100
mPORTA_BIT3: equ %00001000
mPORTA_BIT4: equ %00010000
mPORTA_BIT5: equ %00100000
mPORTA_BIT6: equ %01000000
mPORTA_BIT7: equ %10000000
;*** PORTB - Port B Register; 0x00000001 ***
PORTB: equ $00000001 ;*** PORTB - Port B Register; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTB_BIT0: equ 0 ; Port B Bit 0
PORTB_BIT1: equ 1 ; Port B Bit 1
PORTB_BIT2: equ 2 ; Port B Bit 2
PORTB_BIT3: equ 3 ; Port B Bit 3
PORTB_BIT4: equ 4 ; Port B Bit 4
PORTB_BIT5: equ 5 ; Port B Bit 5
PORTB_BIT6: equ 6 ; Port B Bit 6
PORTB_BIT7: equ 7 ; Port B Bit 7
; bit position masks
mPORTB_BIT0: equ %00000001
mPORTB_BIT1: equ %00000010
mPORTB_BIT2: equ %00000100
mPORTB_BIT3: equ %00001000
mPORTB_BIT4: equ %00010000
mPORTB_BIT5: equ %00100000
mPORTB_BIT6: equ %01000000
mPORTB_BIT7: equ %10000000
;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
DDRAB: equ $00000002 ;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRAB_BIT0: equ 0 ; Data Direction Port AB Bit 0
DDRAB_BIT1: equ 1 ; Data Direction Port AB Bit 1
DDRAB_BIT2: equ 2 ; Data Direction Port AB Bit 2
DDRAB_BIT3: equ 3 ; Data Direction Port AB Bit 3
DDRAB_BIT4: equ 4 ; Data Direction Port AB Bit 4
DDRAB_BIT5: equ 5 ; Data Direction Port AB Bit 5
DDRAB_BIT6: equ 6 ; Data Direction Port AB Bit 6
DDRAB_BIT7: equ 7 ; Data Direction Port AB Bit 7
DDRAB_BIT8: equ 8 ; Data Direction Port AB Bit 8
DDRAB_BIT9: equ 9 ; Data Direction Port AB Bit 9
DDRAB_BIT10: equ 10 ; Data Direction Port AB Bit 10
DDRAB_BIT11: equ 11 ; Data Direction Port AB Bit 11
DDRAB_BIT12: equ 12 ; Data Direction Port AB Bit 12
DDRAB_BIT13: equ 13 ; Data Direction Port AB Bit 13
DDRAB_BIT14: equ 14 ; Data Direction Port AB Bit 14
DDRAB_BIT15: equ 15 ; Data Direction Port AB Bit 15
; bit position masks
mDDRAB_BIT0: equ %00000001
mDDRAB_BIT1: equ %00000010
mDDRAB_BIT2: equ %00000100
mDDRAB_BIT3: equ %00001000
mDDRAB_BIT4: equ %00010000
mDDRAB_BIT5: equ %00100000
mDDRAB_BIT6: equ %01000000
mDDRAB_BIT7: equ %10000000
mDDRAB_BIT8: equ %100000000
mDDRAB_BIT9: equ %1000000000
mDDRAB_BIT10: equ %10000000000
mDDRAB_BIT11: equ %100000000000
mDDRAB_BIT12: equ %1000000000000
mDDRAB_BIT13: equ %10000000000000
mDDRAB_BIT14: equ %100000000000000
mDDRAB_BIT15: equ %1000000000000000
;*** DDRA - Port A Data Direction Register; 0x00000002 ***
DDRA: equ $00000002 ;*** DDRA - Port A Data Direction Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRA_BIT0: equ 0 ; Data Direction Port A Bit 0
DDRA_BIT1: equ 1 ; Data Direction Port A Bit 1
DDRA_BIT2: equ 2 ; Data Direction Port A Bit 2
DDRA_BIT3: equ 3 ; Data Direction Port A Bit 3
DDRA_BIT4: equ 4 ; Data Direction Port A Bit 4
DDRA_BIT5: equ 5 ; Data Direction Port A Bit 5
DDRA_BIT6: equ 6 ; Data Direction Port A Bit 6
DDRA_BIT7: equ 7 ; Data Direction Port A Bit 7
; bit position masks
mDDRA_BIT0: equ %00000001
mDDRA_BIT1: equ %00000010
mDDRA_BIT2: equ %00000100
mDDRA_BIT3: equ %00001000
mDDRA_BIT4: equ %00010000
mDDRA_BIT5: equ %00100000
mDDRA_BIT6: equ %01000000
mDDRA_BIT7: equ %10000000
;*** DDRB - Port B Data Direction Register; 0x00000003 ***
DDRB: equ $00000003 ;*** DDRB - Port B Data Direction Register; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRB_BIT0: equ 0 ; Data Direction Port B Bit 0
DDRB_BIT1: equ 1 ; Data Direction Port B Bit 1
DDRB_BIT2: equ 2 ; Data Direction Port B Bit 2
DDRB_BIT3: equ 3 ; Data Direction Port B Bit 3
DDRB_BIT4: equ 4 ; Data Direction Port B Bit 4
DDRB_BIT5: equ 5 ; Data Direction Port B Bit 5
DDRB_BIT6: equ 6 ; Data Direction Port B Bit 6
DDRB_BIT7: equ 7 ; Data Direction Port B Bit 7
; bit position masks
mDDRB_BIT0: equ %00000001
mDDRB_BIT1: equ %00000010
mDDRB_BIT2: equ %00000100
mDDRB_BIT3: equ %00001000
mDDRB_BIT4: equ %00010000
mDDRB_BIT5: equ %00100000
mDDRB_BIT6: equ %01000000
mDDRB_BIT7: equ %10000000
;*** PORTE - Port E Register; 0x00000008 ***
PORTE: equ $00000008 ;*** PORTE - Port E Register; 0x00000008 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTE_BIT0: equ 0 ; Port E Bit 0
PORTE_BIT1: equ 1 ; Port E Bit 1
PORTE_BIT2: equ 2 ; Port E Bit 2
PORTE_BIT3: equ 3 ; Port E Bit 3
PORTE_BIT4: equ 4 ; Port E Bit 4
PORTE_BIT5: equ 5 ; Port E Bit 5
PORTE_BIT6: equ 6 ; Port E Bit 6
PORTE_BIT7: equ 7 ; Port E Bit 7
; bit position masks
mPORTE_BIT0: equ %00000001
mPORTE_BIT1: equ %00000010
mPORTE_BIT2: equ %00000100
mPORTE_BIT3: equ %00001000
mPORTE_BIT4: equ %00010000
mPORTE_BIT5: equ %00100000
mPORTE_BIT6: equ %01000000
mPORTE_BIT7: equ %10000000
;*** DDRE - Port E Data Direction Register; 0x00000009 ***
DDRE: equ $00000009 ;*** DDRE - Port E Data Direction Register; 0x00000009 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRE_BIT2: equ 2 ; Data Direction Port E Bit 2
DDRE_BIT3: equ 3 ; Data Direction Port E Bit 3
DDRE_BIT4: equ 4 ; Data Direction Port E Bit 4
DDRE_BIT5: equ 5 ; Data Direction Port E Bit 5
DDRE_BIT6: equ 6 ; Data Direction Port E Bit 6
DDRE_BIT7: equ 7 ; Data Direction Port E Bit 7
; bit position masks
mDDRE_BIT2: equ %00000100
mDDRE_BIT3: equ %00001000
mDDRE_BIT4: equ %00010000
mDDRE_BIT5: equ %00100000
mDDRE_BIT6: equ %01000000
mDDRE_BIT7: equ %10000000
;*** PEAR - Port E Assignment Register; 0x0000000A ***
PEAR: equ $0000000A ;*** PEAR - Port E Assignment Register; 0x0000000A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PEAR_RDWE: equ 2 ; Read / Write Enable
PEAR_LSTRE: equ 3 ; Low Strobe (LSTRB) Enable
PEAR_NECLK: equ 4 ; No External E Clock
PEAR_PIPOE: equ 5 ; Pipe Status Signal Output Enable
PEAR_NOACCE: equ 7 ; CPU No Access Output Enable
; bit position masks
mPEAR_RDWE: equ %00000100
mPEAR_LSTRE: equ %00001000
mPEAR_NECLK: equ %00010000
mPEAR_PIPOE: equ %00100000
mPEAR_NOACCE: equ %10000000
;*** MODE - Mode Register; 0x0000000B ***
MODE: equ $0000000B ;*** MODE - Mode Register; 0x0000000B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MODE_EME: equ 0 ; Emulate Port E
MODE_EMK: equ 1 ; Emulate Port K
MODE_IVIS: equ 3 ; Internal Visibility
MODE_MODA: equ 5 ; Mode Select Bit A
MODE_MODB: equ 6 ; Mode Select Bit B
MODE_MODC: equ 7 ; Mode Select Bit C
; bit position masks
mMODE_EME: equ %00000001
mMODE_EMK: equ %00000010
mMODE_IVIS: equ %00001000
mMODE_MODA: equ %00100000
mMODE_MODB: equ %01000000
mMODE_MODC: equ %10000000
;*** PUCR - Pull-Up Control Register; 0x0000000C ***
PUCR: equ $0000000C ;*** PUCR - Pull-Up Control Register; 0x0000000C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PUCR_PUPAE: equ 0 ; Pull-Up Port A Enable
PUCR_PUPBE: equ 1 ; Pull-Up Port B Enable
PUCR_PUPEE: equ 4 ; Pull-Up Port E Enable
PUCR_PUPKE: equ 7 ; Pull-Up Port K Enable
; bit position masks
mPUCR_PUPAE: equ %00000001
mPUCR_PUPBE: equ %00000010
mPUCR_PUPEE: equ %00010000
mPUCR_PUPKE: equ %10000000
;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
RDRIV: equ $0000000D ;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
RDRIV_RDPA: equ 0 ; Reduced Drive of Port A
RDRIV_RDPB: equ 1 ; Reduced Drive of Port B
RDRIV_RDPE: equ 4 ; Reduced Drive of Port E
RDRIV_RDPK: equ 7 ; Reduced Drive of Port K
; bit position masks
mRDRIV_RDPA: equ %00000001
mRDRIV_RDPB: equ %00000010
mRDRIV_RDPE: equ %00010000
mRDRIV_RDPK: equ %10000000
;*** EBICTL - External Bus Interface Control; 0x0000000E ***
EBICTL: equ $0000000E ;*** EBICTL - External Bus Interface Control; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
EBICTL_ESTR: equ 0 ; E Stretches
; bit position masks
mEBICTL_ESTR: equ %00000001
;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
INITRM: equ $00000010 ;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INITRM_RAMHAL: equ 0 ; Internal RAM map alignment
INITRM_RAM11: equ 3 ; Internal RAM map position Bit 11
INITRM_RAM12: equ 4 ; Internal RAM map position Bit 12
INITRM_RAM13: equ 5 ; Internal RAM map position Bit 13
INITRM_RAM14: equ 6 ; Internal RAM map position Bit 14
INITRM_RAM15: equ 7 ; Internal RAM map position Bit 15
; bit position masks
mINITRM_RAMHAL: equ %00000001
mINITRM_RAM11: equ %00001000
mINITRM_RAM12: equ %00010000
mINITRM_RAM13: equ %00100000
mINITRM_RAM14: equ %01000000
mINITRM_RAM15: equ %10000000
;*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***
INITRG: equ $00000011 ;*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INITRG_REG11: equ 3 ; Internal Registers Map Position Bit 11
INITRG_REG12: equ 4 ; Internal Registers Map Position Bit 12
INITRG_REG13: equ 5 ; Internal Registers Map Position Bit 13
INITRG_REG14: equ 6 ; Internal Registers Map Position Bit 14
; bit position masks
mINITRG_REG11: equ %00001000
mINITRG_REG12: equ %00010000
mINITRG_REG13: equ %00100000
mINITRG_REG14: equ %01000000
;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
MISC: equ $00000013 ;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MISC_ROMON: equ 0 ; Enable Flash EEPROM
MISC_ROMHM: equ 1 ; Flash EEPROM only in second half of memory map
MISC_EXSTR0: equ 2 ; External Access Stretch Bit 0
MISC_EXSTR1: equ 3 ; External Access Stretch Bit 1
; bit position masks
mMISC_ROMON: equ %00000001
mMISC_ROMHM: equ %00000010
mMISC_EXSTR0: equ %00000100
mMISC_EXSTR1: equ %00001000
;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
ITCR: equ $00000015 ;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ITCR_ADR0: equ 0 ; Test register select Bit 0
ITCR_ADR1: equ 1 ; Test register select Bit 1
ITCR_ADR2: equ 2 ; Test register select Bit 2
ITCR_ADR3: equ 3 ; Test register select Bit 3
ITCR_WRTINT: equ 4 ; Write to the Interrupt Test Registers
; bit position masks
mITCR_ADR0: equ %00000001
mITCR_ADR1: equ %00000010
mITCR_ADR2: equ %00000100
mITCR_ADR3: equ %00001000
mITCR_WRTINT: equ %00010000
;*** ITEST - Interrupt Test Register; 0x00000016 ***
ITEST: equ $00000016 ;*** ITEST - Interrupt Test Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ITEST_INT0: equ 0 ; Interrupt Test Register Bit 0
ITEST_INT2: equ 1 ; Interrupt Test Register Bit 1
ITEST_INT4: equ 2 ; Interrupt Test Register Bit 2
ITEST_INT6: equ 3 ; Interrupt Test Register Bit 3
ITEST_INT8: equ 4 ; Interrupt Test Register Bit 4
ITEST_INTA: equ 5 ; Interrupt Test Register Bit 5
ITEST_INTC: equ 6 ; Interrupt Test Register Bit 6
ITEST_INTE: equ 7 ; Interrupt Test Register Bit 7
; bit position masks
mITEST_INT0: equ %00000001
mITEST_INT2: equ %00000010
mITEST_INT4: equ %00000100
mITEST_INT6: equ %00001000
mITEST_INT8: equ %00010000
mITEST_INTA: equ %00100000
mITEST_INTC: equ %01000000
mITEST_INTE: equ %10000000
;*** VREGCTRL - VREG_3V3 - Control Register; 0x00000019 ***
VREGCTRL: equ $00000019 ;*** VREGCTRL - VREG_3V3 - Control Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
VREGCTRL_LVIF: equ 0 ; Low Voltage Interrupt Flag
VREGCTRL_LVIE: equ 1 ; Low Voltage Interrupt Enable Bit
VREGCTRL_LVDS: equ 2 ; Low Voltage Detect Status Bit
; bit position masks
mVREGCTRL_LVIF: equ %00000001
mVREGCTRL_LVIE: equ %00000010
mVREGCTRL_LVDS: equ %00000100
;*** PARTID - Part ID Register; 0x0000001A ***
PARTID: equ $0000001A ;*** PARTID - Part ID Register; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTID_ID0: equ 0 ; Part ID Register Bit 0
PARTID_ID1: equ 1 ; Part ID Register Bit 1
PARTID_ID2: equ 2 ; Part ID Register Bit 2
PARTID_ID3: equ 3 ; Part ID Register Bit 3
PARTID_ID4: equ 4 ; Part ID Register Bit 4
PARTID_ID5: equ 5 ; Part ID Register Bit 5
PARTID_ID6: equ 6 ; Part ID Register Bit 6
PARTID_ID7: equ 7 ; Part ID Register Bit 7
PARTID_ID8: equ 8 ; Part ID Register Bit 8
PARTID_ID9: equ 9 ; Part ID Register Bit 9
PARTID_ID10: equ 10 ; Part ID Register Bit 10
PARTID_ID11: equ 11 ; Part ID Register Bit 11
PARTID_ID12: equ 12 ; Part ID Register Bit 12
PARTID_ID13: equ 13 ; Part ID Register Bit 13
PARTID_ID14: equ 14 ; Part ID Register Bit 14
PARTID_ID15: equ 15 ; Part ID Register Bit 15
; bit position masks
mPARTID_ID0: equ %00000001
mPARTID_ID1: equ %00000010
mPARTID_ID2: equ %00000100
mPARTID_ID3: equ %00001000
mPARTID_ID4: equ %00010000
mPARTID_ID5: equ %00100000
mPARTID_ID6: equ %01000000
mPARTID_ID7: equ %10000000
mPARTID_ID8: equ %100000000
mPARTID_ID9: equ %1000000000
mPARTID_ID10: equ %10000000000
mPARTID_ID11: equ %100000000000
mPARTID_ID12: equ %1000000000000
mPARTID_ID13: equ %10000000000000
mPARTID_ID14: equ %100000000000000
mPARTID_ID15: equ %1000000000000000
;*** PARTIDH - Part ID Register High; 0x0000001A ***
PARTIDH: equ $0000001A ;*** PARTIDH - Part ID Register High; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTIDH_ID8: equ 0 ; Part ID Register Bit 8
PARTIDH_ID9: equ 1 ; Part ID Register Bit 9
PARTIDH_ID10: equ 2 ; Part ID Register Bit 10
PARTIDH_ID11: equ 3 ; Part ID Register Bit 11
PARTIDH_ID12: equ 4 ; Part ID Register Bit 12
PARTIDH_ID13: equ 5 ; Part ID Register Bit 13
PARTIDH_ID14: equ 6 ; Part ID Register Bit 14
PARTIDH_ID15: equ 7 ; Part ID Register Bit 15
; bit position masks
mPARTIDH_ID8: equ %00000001
mPARTIDH_ID9: equ %00000010
mPARTIDH_ID10: equ %00000100
mPARTIDH_ID11: equ %00001000
mPARTIDH_ID12: equ %00010000
mPARTIDH_ID13: equ %00100000
mPARTIDH_ID14: equ %01000000
mPARTIDH_ID15: equ %10000000
;*** PARTIDL - Part ID Register Low; 0x0000001B ***
PARTIDL: equ $0000001B ;*** PARTIDL - Part ID Register Low; 0x0000001B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTIDL_ID0: equ 0 ; Part ID Register Bit 0
PARTIDL_ID1: equ 1 ; Part ID Register Bit 1
PARTIDL_ID2: equ 2 ; Part ID Register Bit 2
PARTIDL_ID3: equ 3 ; Part ID Register Bit 3
PARTIDL_ID4: equ 4 ; Part ID Register Bit 4
PARTIDL_ID5: equ 5 ; Part ID Register Bit 5
PARTIDL_ID6: equ 6 ; Part ID Register Bit 6
PARTIDL_ID7: equ 7 ; Part ID Register Bit 7
; bit position masks
mPARTIDL_ID0: equ %00000001
mPARTIDL_ID1: equ %00000010
mPARTIDL_ID2: equ %00000100
mPARTIDL_ID3: equ %00001000
mPARTIDL_ID4: equ %00010000
mPARTIDL_ID5: equ %00100000
mPARTIDL_ID6: equ %01000000
mPARTIDL_ID7: equ %10000000
;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
MEMSIZ0: equ $0000001C ;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MEMSIZ0_ram_sw0: equ 0 ; Allocated System RAM Memory Space Bit 0
MEMSIZ0_ram_sw1: equ 1 ; Allocated System RAM Memory Space Bit 1
MEMSIZ0_ram_sw2: equ 2 ; Allocated System RAM Memory Space Bit 2
MEMSIZ0_eep_sw0: equ 4 ; Allocated EEPROM Memory Space Bit 0
MEMSIZ0_eep_sw1: equ 5 ; Allocated EEPROM Memory Space Bit 1
MEMSIZ0_reg_sw0: equ 7 ; Allocated System Register Space
; bit position masks
mMEMSIZ0_ram_sw0: equ %00000001
mMEMSIZ0_ram_sw1: equ %00000010
mMEMSIZ0_ram_sw2: equ %00000100
mMEMSIZ0_eep_sw0: equ %00010000
mMEMSIZ0_eep_sw1: equ %00100000
mMEMSIZ0_reg_sw0: equ %10000000
;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
MEMSIZ1: equ $0000001D ;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MEMSIZ1_pag_sw0: equ 0 ; Allocated Off-Chip Memory Options Bit 0
MEMSIZ1_pag_sw1: equ 1 ; Allocated Off-Chip Memory Options Bit 1
MEMSIZ1_rom_sw0: equ 6 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 0
MEMSIZ1_rom_sw1: equ 7 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 1
; bit position masks
mMEMSIZ1_pag_sw0: equ %00000001
mMEMSIZ1_pag_sw1: equ %00000010
mMEMSIZ1_rom_sw0: equ %01000000
mMEMSIZ1_rom_sw1: equ %10000000
;*** INTCR - Interrupt Control Register; 0x0000001E ***
INTCR: equ $0000001E ;*** INTCR - Interrupt Control Register; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INTCR_IRQEN: equ 6 ; External IRQ Enable
INTCR_IRQE: equ 7 ; IRQ Select Edge Sensitive Only
; bit position masks
mINTCR_IRQEN: equ %01000000
mINTCR_IRQE: equ %10000000
;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
HPRIO: equ $0000001F ;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
HPRIO_PSEL1: equ 1 ; Highest Priority I Interrupt Bit 1
HPRIO_PSEL2: equ 2 ; Highest Priority I Interrupt Bit 2
HPRIO_PSEL3: equ 3 ; Highest Priority I Interrupt Bit 3
HPRIO_PSEL4: equ 4 ; Highest Priority I Interrupt Bit 4
HPRIO_PSEL5: equ 5 ; Highest Priority I Interrupt Bit 5
HPRIO_PSEL6: equ 6 ; Highest Priority I Interrupt Bit 6
HPRIO_PSEL7: equ 7 ; Highest Priority I Interrupt Bit 7
; bit position masks
mHPRIO_PSEL1: equ %00000010
mHPRIO_PSEL2: equ %00000100
mHPRIO_PSEL3: equ %00001000
mHPRIO_PSEL4: equ %00010000
mHPRIO_PSEL5: equ %00100000
mHPRIO_PSEL6: equ %01000000
mHPRIO_PSEL7: equ %10000000
;*** DBGC1 - Debug Control Register 1; 0x00000020 ***
DBGC1: equ $00000020 ;*** DBGC1 - Debug Control Register 1; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGC1_CAPMOD0: equ 0 ; Capture Mode Field, bit 0
DBGC1_CAPMOD1: equ 1 ; Capture Mode Field, bit 1
DBGC1_DBGBRK: equ 3 ; DBG Breakpoint Enable Bit
DBGC1_BEGIN: equ 4 ; Begin/End Trigger Bit
DBGC1_TRGSEL: equ 5 ; Trigger Selection Bit
DBGC1_ARM: equ 6 ; Arm Bit
DBGC1_DBGEN: equ 7 ; DBG Mode Enable Bit
; bit position masks
mDBGC1_CAPMOD0: equ %00000001
mDBGC1_CAPMOD1: equ %00000010
mDBGC1_DBGBRK: equ %00001000
mDBGC1_BEGIN: equ %00010000
mDBGC1_TRGSEL: equ %00100000
mDBGC1_ARM: equ %01000000
mDBGC1_DBGEN: equ %10000000
;*** DBGSC - Debug Status and Control Register; 0x00000021 ***
DBGSC: equ $00000021 ;*** DBGSC - Debug Status and Control Register; 0x00000021 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGSC_TRG0: equ 0 ; Trigger Mode Bits, bit 0
DBGSC_TRG1: equ 1 ; Trigger Mode Bits, bit 1
DBGSC_TRG2: equ 2 ; Trigger Mode Bits, bit 2
DBGSC_TRG3: equ 3 ; Trigger Mode Bits, bit 3
DBGSC_CF: equ 5 ; Comparator C Match Flag
DBGSC_BF: equ 6 ; Trigger B Match Flag
DBGSC_AF: equ 7 ; Trigger A Match Flag
; bit position masks
mDBGSC_TRG0: equ %00000001
mDBGSC_TRG1: equ %00000010
mDBGSC_TRG2: equ %00000100
mDBGSC_TRG3: equ %00001000
mDBGSC_CF: equ %00100000
mDBGSC_BF: equ %01000000
mDBGSC_AF: equ %10000000
;*** DBGTB - Debug Trace Buffer Register; 0x00000022 ***
DBGTB: equ $00000022 ;*** DBGTB - Debug Trace Buffer Register; 0x00000022 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGTB_BIT0: equ 0 ; Trace Buffer Data Bit 0
DBGTB_BIT1: equ 1 ; Trace Buffer Data Bit 1
DBGTB_BIT2: equ 2 ; Trace Buffer Data Bit 2
DBGTB_BIT3: equ 3 ; Trace Buffer Data Bit 3
DBGTB_BIT4: equ 4 ; Trace Buffer Data Bit 4
DBGTB_BIT5: equ 5 ; Trace Buffer Data Bit 5
DBGTB_BIT6: equ 6 ; Trace Buffer Data Bit 6
DBGTB_BIT7: equ 7 ; Trace Buffer Data Bit 7
DBGTB_BIT8: equ 8 ; Trace Buffer Data Bit 8
DBGTB_BIT9: equ 9 ; Trace Buffer Data Bit 9
DBGTB_BIT10: equ 10 ; Trace Buffer Data Bit 10
DBGTB_BIT11: equ 11 ; Trace Buffer Data Bit 11
DBGTB_BIT12: equ 12 ; Trace Buffer Data Bit 12
DBGTB_BIT13: equ 13 ; Trace Buffer Data Bit 13
DBGTB_BIT14: equ 14 ; Trace Buffer Data Bit 14
DBGTB_BIT15: equ 15 ; Trace Buffer Data Bit 15
; bit position masks
mDBGTB_BIT0: equ %00000001
mDBGTB_BIT1: equ %00000010
mDBGTB_BIT2: equ %00000100
mDBGTB_BIT3: equ %00001000
mDBGTB_BIT4: equ %00010000
mDBGTB_BIT5: equ %00100000
mDBGTB_BIT6: equ %01000000
mDBGTB_BIT7: equ %10000000
mDBGTB_BIT8: equ %100000000
mDBGTB_BIT9: equ %1000000000
mDBGTB_BIT10: equ %10000000000
mDBGTB_BIT11: equ %100000000000
mDBGTB_BIT12: equ %1000000000000
mDBGTB_BIT13: equ %10000000000000
mDBGTB_BIT14: equ %100000000000000
mDBGTB_BIT15: equ %1000000000000000
;*** DBGTBH - Debug Trace Buffer Register High; 0x00000022 ***
DBGTBH: equ $00000022 ;*** DBGTBH - Debug Trace Buffer Register High; 0x00000022 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGTBH_BIT8: equ 0 ; Trace Buffer Data Bit 8
DBGTBH_BIT9: equ 1 ; Trace Buffer Data Bit 9
DBGTBH_BIT10: equ 2 ; Trace Buffer Data Bit 10
DBGTBH_BIT11: equ 3 ; Trace Buffer Data Bit 11
DBGTBH_BIT12: equ 4 ; Trace Buffer Data Bit 12
DBGTBH_BIT13: equ 5 ; Trace Buffer Data Bit 13
DBGTBH_BIT14: equ 6 ; Trace Buffer Data Bit 14
DBGTBH_BIT15: equ 7 ; Trace Buffer Data Bit 15
; bit position masks
mDBGTBH_BIT8: equ %00000001
mDBGTBH_BIT9: equ %00000010
mDBGTBH_BIT10: equ %00000100
mDBGTBH_BIT11: equ %00001000
mDBGTBH_BIT12: equ %00010000
mDBGTBH_BIT13: equ %00100000
mDBGTBH_BIT14: equ %01000000
mDBGTBH_BIT15: equ %10000000
;*** DBGTBL - Debug Trace Buffer Register Low; 0x00000023 ***
DBGTBL: equ $00000023 ;*** DBGTBL - Debug Trace Buffer Register Low; 0x00000023 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGTBL_BIT0: equ 0 ; Trace Buffer Data Bit 0
DBGTBL_BIT1: equ 1 ; Trace Buffer Data Bit 1
DBGTBL_BIT2: equ 2 ; Trace Buffer Data Bit 2
DBGTBL_BIT3: equ 3 ; Trace Buffer Data Bit 3
DBGTBL_BIT4: equ 4 ; Trace Buffer Data Bit 4
DBGTBL_BIT5: equ 5 ; Trace Buffer Data Bit 5
DBGTBL_BIT6: equ 6 ; Trace Buffer Data Bit 6
DBGTBL_BIT7: equ 7 ; Trace Buffer Data Bit 7
; bit position masks
mDBGTBL_BIT0: equ %00000001
mDBGTBL_BIT1: equ %00000010
mDBGTBL_BIT2: equ %00000100
mDBGTBL_BIT3: equ %00001000
mDBGTBL_BIT4: equ %00010000
mDBGTBL_BIT5: equ %00100000
mDBGTBL_BIT6: equ %01000000
mDBGTBL_BIT7: equ %10000000
;*** DBGCNT - Debug Count Register; 0x00000024 ***
DBGCNT: equ $00000024 ;*** DBGCNT - Debug Count Register; 0x00000024 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCNT_CNT0: equ 0 ; Count Value, bit 0
DBGCNT_CNT1: equ 1 ; Count Value, bit 1
DBGCNT_CNT2: equ 2 ; Count Value, bit 2
DBGCNT_CNT3: equ 3 ; Count Value, bit 3
DBGCNT_CNT4: equ 4 ; Count Value, bit 4
DBGCNT_CNT5: equ 5 ; Count Value, bit 5
DBGCNT_TBF: equ 7 ; Trace Buffer Full
; bit position masks
mDBGCNT_CNT0: equ %00000001
mDBGCNT_CNT1: equ %00000010
mDBGCNT_CNT2: equ %00000100
mDBGCNT_CNT3: equ %00001000
mDBGCNT_CNT4: equ %00010000
mDBGCNT_CNT5: equ %00100000
mDBGCNT_TBF: equ %10000000
;*** DBGCCX - Debug Comparator C Extended Register; 0x00000025 ***
DBGCCX: equ $00000025 ;*** DBGCCX - Debug Comparator C Extended Register; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCCX_EXTCMP0: equ 0 ; Comparator C Extended Compare Bits, bit 0
DBGCCX_EXTCMP1: equ 1 ; Comparator C Extended Compare Bits, bit 1
DBGCCX_EXTCMP2: equ 2 ; Comparator C Extended Compare Bits, bit 2
DBGCCX_EXTCMP3: equ 3 ; Comparator C Extended Compare Bits, bit 3
DBGCCX_EXTCMP4: equ 4 ; Comparator C Extended Compare Bits, bit 4
DBGCCX_EXTCMP5: equ 5 ; Comparator C Extended Compare Bits, bit 5
DBGCCX_PAGSEL0: equ 6 ; Page Selector Field, bit 0
DBGCCX_PAGSEL1: equ 7 ; Page Selector Field, bit 1
; bit position masks
mDBGCCX_EXTCMP0: equ %00000001
mDBGCCX_EXTCMP1: equ %00000010
mDBGCCX_EXTCMP2: equ %00000100
mDBGCCX_EXTCMP3: equ %00001000
mDBGCCX_EXTCMP4: equ %00010000
mDBGCCX_EXTCMP5: equ %00100000
mDBGCCX_PAGSEL0: equ %01000000
mDBGCCX_PAGSEL1: equ %10000000
;*** DBGCC - Debug Comparator C Register; 0x00000026 ***
DBGCC: equ $00000026 ;*** DBGCC - Debug Comparator C Register; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCC_BIT0: equ 0 ; Comparator C Compare Bit 0
DBGCC_BIT1: equ 1 ; Comparator C Compare Bit 1
DBGCC_BIT2: equ 2 ; Comparator C Compare Bit 2
DBGCC_BIT3: equ 3 ; Comparator C Compare Bit 3
DBGCC_BIT4: equ 4 ; Comparator C Compare Bit 4
DBGCC_BIT5: equ 5 ; Comparator C Compare Bit 5
DBGCC_BIT6: equ 6 ; Comparator C Compare Bit 6
DBGCC_BIT7: equ 7 ; Comparator C Compare Bit 7
DBGCC_BIT8: equ 8 ; Comparator C Compare Bit 8
DBGCC_BIT9: equ 9 ; Comparator C Compare Bit 9
DBGCC_BIT10: equ 10 ; Comparator C Compare Bit 10
DBGCC_BIT11: equ 11 ; Comparator C Compare Bit 11
DBGCC_BIT12: equ 12 ; Comparator C Compare Bit 12
DBGCC_BIT13: equ 13 ; Comparator C Compare Bit 13
DBGCC_BIT14: equ 14 ; Comparator C Compare Bit 14
DBGCC_BIT15: equ 15 ; Comparator C Compare Bit 15
; bit position masks
mDBGCC_BIT0: equ %00000001
mDBGCC_BIT1: equ %00000010
mDBGCC_BIT2: equ %00000100
mDBGCC_BIT3: equ %00001000
mDBGCC_BIT4: equ %00010000
mDBGCC_BIT5: equ %00100000
mDBGCC_BIT6: equ %01000000
mDBGCC_BIT7: equ %10000000
mDBGCC_BIT8: equ %100000000
mDBGCC_BIT9: equ %1000000000
mDBGCC_BIT10: equ %10000000000
mDBGCC_BIT11: equ %100000000000
mDBGCC_BIT12: equ %1000000000000
mDBGCC_BIT13: equ %10000000000000
mDBGCC_BIT14: equ %100000000000000
mDBGCC_BIT15: equ %1000000000000000
;*** DBGCCH - Debug Comparator C Register High; 0x00000026 ***
DBGCCH: equ $00000026 ;*** DBGCCH - Debug Comparator C Register High; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCCH_BIT8: equ 0 ; Comparator C Compare Bit 8
DBGCCH_BIT9: equ 1 ; Comparator C Compare Bit 9
DBGCCH_BIT10: equ 2 ; Comparator C Compare Bit 10
DBGCCH_BIT11: equ 3 ; Comparator C Compare Bit 11
DBGCCH_BIT12: equ 4 ; Comparator C Compare Bit 12
DBGCCH_BIT13: equ 5 ; Comparator C Compare Bit 13
DBGCCH_BIT14: equ 6 ; Comparator C Compare Bit 14
DBGCCH_BIT15: equ 7 ; Comparator C Compare Bit 15
; bit position masks
mDBGCCH_BIT8: equ %00000001
mDBGCCH_BIT9: equ %00000010
mDBGCCH_BIT10: equ %00000100
mDBGCCH_BIT11: equ %00001000
mDBGCCH_BIT12: equ %00010000
mDBGCCH_BIT13: equ %00100000
mDBGCCH_BIT14: equ %01000000
mDBGCCH_BIT15: equ %10000000
;*** DBGCCL - Debug Comparator C Register Low; 0x00000027 ***
DBGCCL: equ $00000027 ;*** DBGCCL - Debug Comparator C Register Low; 0x00000027 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCCL_BIT0: equ 0 ; Comparator C Compare Bit 0
DBGCCL_BIT1: equ 1 ; Comparator C Compare Bit 1
DBGCCL_BIT2: equ 2 ; Comparator C Compare Bit 2
DBGCCL_BIT3: equ 3 ; Comparator C Compare Bit 3
DBGCCL_BIT4: equ 4 ; Comparator C Compare Bit 4
DBGCCL_BIT5: equ 5 ; Comparator C Compare Bit 5
DBGCCL_BIT6: equ 6 ; Comparator C Compare Bit 6
DBGCCL_BIT7: equ 7 ; Comparator C Compare Bit 7
; bit position masks
mDBGCCL_BIT0: equ %00000001
mDBGCCL_BIT1: equ %00000010
mDBGCCL_BIT2: equ %00000100
mDBGCCL_BIT3: equ %00001000
mDBGCCL_BIT4: equ %00010000
mDBGCCL_BIT5: equ %00100000
mDBGCCL_BIT6: equ %01000000
mDBGCCL_BIT7: equ %10000000
;*** DBGC2 - Debug Control Register 2; 0x00000028 ***
DBGC2: equ $00000028 ;*** DBGC2 - Debug Control Register 2; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGC2_RWC: equ 0 ; Read/Write Comparator C Value Bit
DBGC2_RWCEN: equ 1 ; Read/Write Comparator C Enable Bit
DBGC2_TAGC: equ 2 ; Comparator C Tag Select
DBGC2_BKCEN: equ 3 ; Breakpoint Comparator C Enable Bit
DBGC2_TAGAB: equ 4 ; Comparator A/B Tag Select
DBGC2_BDM: equ 5 ; Background Debug Mode Enable
DBGC2_FULL: equ 6 ; Full Breakpoint Mode Enable
DBGC2_BKABEN: equ 7 ; Breakpoint Using Comparator A and B Enable
; bit position masks
mDBGC2_RWC: equ %00000001
mDBGC2_RWCEN: equ %00000010
mDBGC2_TAGC: equ %00000100
mDBGC2_BKCEN: equ %00001000
mDBGC2_TAGAB: equ %00010000
mDBGC2_BDM: equ %00100000
mDBGC2_FULL: equ %01000000
mDBGC2_BKABEN: equ %10000000
;*** DBGC3 - Debug Control Register 3; 0x00000029 ***
DBGC3: equ $00000029 ;*** DBGC3 - Debug Control Register 3; 0x00000029 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGC3_RWB: equ 0 ; Read/Write Comparator B Value Bit
DBGC3_RWBEN: equ 1 ; Read/Write Comparator B Enable Bit
DBGC3_RWA: equ 2 ; Read/Write Comparator A Value Bit
DBGC3_RWAEN: equ 3 ; Read/Write Comparator A Enable Bit
DBGC3_BKBMBL: equ 4 ; Breakpoint Mask Low Byte for Second Address
DBGC3_BKBMBH: equ 5 ; Breakpoint Mask High Byte for Second Address
DBGC3_BKAMBL: equ 6 ; Breakpoint Mask Low Byte for First Address
DBGC3_BKAMBH: equ 7 ; Breakpoint Mask High Byte for First Address
; bit position masks
mDBGC3_RWB: equ %00000001
mDBGC3_RWBEN: equ %00000010
mDBGC3_RWA: equ %00000100
mDBGC3_RWAEN: equ %00001000
mDBGC3_BKBMBL: equ %00010000
mDBGC3_BKBMBH: equ %00100000
mDBGC3_BKAMBL: equ %01000000
mDBGC3_BKAMBH: equ %10000000
;*** DBGCAX - Debug Comparator A Extended Register; 0x0000002A ***
DBGCAX: equ $0000002A ;*** DBGCAX - Debug Comparator A Extended Register; 0x0000002A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCAX_EXTCMP0: equ 0 ; Comparator A Extended Compare Bits, bit 0
DBGCAX_EXTCMP1: equ 1 ; Comparator A Extended Compare Bits, bit 1
DBGCAX_EXTCMP2: equ 2 ; Comparator A Extended Compare Bits, bit 2
DBGCAX_EXTCMP3: equ 3 ; Comparator A Extended Compare Bits, bit 3
DBGCAX_EXTCMP4: equ 4 ; Comparator A Extended Compare Bits, bit 4
DBGCAX_EXTCMP5: equ 5 ; Comparator A Extended Compare Bits, bit 5
DBGCAX_PAGSEL0: equ 6 ; Page Selector Field, bit 0
DBGCAX_PAGSEL1: equ 7 ; Page Selector Field, bit 1
; bit position masks
mDBGCAX_EXTCMP0: equ %00000001
mDBGCAX_EXTCMP1: equ %00000010
mDBGCAX_EXTCMP2: equ %00000100
mDBGCAX_EXTCMP3: equ %00001000
mDBGCAX_EXTCMP4: equ %00010000
mDBGCAX_EXTCMP5: equ %00100000
mDBGCAX_PAGSEL0: equ %01000000
mDBGCAX_PAGSEL1: equ %10000000
;*** DBGCA - Debug Comparator A Register; 0x0000002B ***
DBGCA: equ $0000002B ;*** DBGCA - Debug Comparator A Register; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCA_BIT0: equ 0 ; Comparator A Compare Bit 0
DBGCA_BIT1: equ 1 ; Comparator A Compare Bit 1
DBGCA_BIT2: equ 2 ; Comparator A Compare Bit 2
DBGCA_BIT3: equ 3 ; Comparator A Compare Bit 3
DBGCA_BIT4: equ 4 ; Comparator A Compare Bit 4
DBGCA_BIT5: equ 5 ; Comparator A Compare Bit 5
DBGCA_BIT6: equ 6 ; Comparator A Compare Bit 6
DBGCA_BIT7: equ 7 ; Comparator A Compare Bit 7
DBGCA_BIT8: equ 8 ; Comparator A Compare Bit 8
DBGCA_BIT9: equ 9 ; Comparator A Compare Bit 9
DBGCA_BIT10: equ 10 ; Comparator A Compare Bit 10
DBGCA_BIT11: equ 11 ; Comparator A Compare Bit 11
DBGCA_BIT12: equ 12 ; Comparator A Compare Bit 12
DBGCA_BIT13: equ 13 ; Comparator A Compare Bit 13
DBGCA_BIT14: equ 14 ; Comparator A Compare Bit 14
DBGCA_BIT15: equ 15 ; Comparator A Compare Bit 15
; bit position masks
mDBGCA_BIT0: equ %00000001
mDBGCA_BIT1: equ %00000010
mDBGCA_BIT2: equ %00000100
mDBGCA_BIT3: equ %00001000
mDBGCA_BIT4: equ %00010000
mDBGCA_BIT5: equ %00100000
mDBGCA_BIT6: equ %01000000
mDBGCA_BIT7: equ %10000000
mDBGCA_BIT8: equ %100000000
mDBGCA_BIT9: equ %1000000000
mDBGCA_BIT10: equ %10000000000
mDBGCA_BIT11: equ %100000000000
mDBGCA_BIT12: equ %1000000000000
mDBGCA_BIT13: equ %10000000000000
mDBGCA_BIT14: equ %100000000000000
mDBGCA_BIT15: equ %1000000000000000
;*** DBGCAH - Debug Comparator A Register High; 0x0000002B ***
DBGCAH: equ $0000002B ;*** DBGCAH - Debug Comparator A Register High; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCAH_BIT8: equ 0 ; Comparator A Compare Bit 8
DBGCAH_BIT9: equ 1 ; Comparator A Compare Bit 9
DBGCAH_BIT10: equ 2 ; Comparator A Compare Bit 10
DBGCAH_BIT11: equ 3 ; Comparator A Compare Bit 11
DBGCAH_BIT12: equ 4 ; Comparator A Compare Bit 12
DBGCAH_BIT13: equ 5 ; Comparator A Compare Bit 13
DBGCAH_BIT14: equ 6 ; Comparator A Compare Bit 14
DBGCAH_BIT15: equ 7 ; Comparator A Compare Bit 15
; bit position masks
mDBGCAH_BIT8: equ %00000001
mDBGCAH_BIT9: equ %00000010
mDBGCAH_BIT10: equ %00000100
mDBGCAH_BIT11: equ %00001000
mDBGCAH_BIT12: equ %00010000
mDBGCAH_BIT13: equ %00100000
mDBGCAH_BIT14: equ %01000000
mDBGCAH_BIT15: equ %10000000
;*** DBGCAL - Debug Comparator A Register Low; 0x0000002C ***
DBGCAL: equ $0000002C ;*** DBGCAL - Debug Comparator A Register Low; 0x0000002C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCAL_BIT0: equ 0 ; Comparator A Compare Bit 0
DBGCAL_BIT1: equ 1 ; Comparator A Compare Bit 1
DBGCAL_BIT2: equ 2 ; Comparator A Compare Bit 2
DBGCAL_BIT3: equ 3 ; Comparator A Compare Bit 3
DBGCAL_BIT4: equ 4 ; Comparator A Compare Bit 4
DBGCAL_BIT5: equ 5 ; Comparator A Compare Bit 5
DBGCAL_BIT6: equ 6 ; Comparator A Compare Bit 6
DBGCAL_BIT7: equ 7 ; Comparator A Compare Bit 7
; bit position masks
mDBGCAL_BIT0: equ %00000001
mDBGCAL_BIT1: equ %00000010
mDBGCAL_BIT2: equ %00000100
mDBGCAL_BIT3: equ %00001000
mDBGCAL_BIT4: equ %00010000
mDBGCAL_BIT5: equ %00100000
mDBGCAL_BIT6: equ %01000000
mDBGCAL_BIT7: equ %10000000
;*** DBGCBX - Debug Comparator B Extended Register; 0x0000002D ***
DBGCBX: equ $0000002D ;*** DBGCBX - Debug Comparator B Extended Register; 0x0000002D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCBX_EXTCMP0: equ 0 ; Comparator B Extended Compare Bits, bit 0
DBGCBX_EXTCMP1: equ 1 ; Comparator B Extended Compare Bits, bit 1
DBGCBX_EXTCMP2: equ 2 ; Comparator B Extended Compare Bits, bit 2
DBGCBX_EXTCMP3: equ 3 ; Comparator B Extended Compare Bits, bit 3
DBGCBX_EXTCMP4: equ 4 ; Comparator B Extended Compare Bits, bit 4
DBGCBX_EXTCMP5: equ 5 ; Comparator B Extended Compare Bits, bit 5
DBGCBX_PAGSEL0: equ 6 ; Page Selector Field, bit 0
DBGCBX_PAGSEL1: equ 7 ; Page Selector Field, bit 1
; bit position masks
mDBGCBX_EXTCMP0: equ %00000001
mDBGCBX_EXTCMP1: equ %00000010
mDBGCBX_EXTCMP2: equ %00000100
mDBGCBX_EXTCMP3: equ %00001000
mDBGCBX_EXTCMP4: equ %00010000
mDBGCBX_EXTCMP5: equ %00100000
mDBGCBX_PAGSEL0: equ %01000000
mDBGCBX_PAGSEL1: equ %10000000
;*** DBGCB - Debug Comparator B Register; 0x0000002E ***
DBGCB: equ $0000002E ;*** DBGCB - Debug Comparator B Register; 0x0000002E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCB_BIT0: equ 0 ; Comparator B High Compare Bit 0
DBGCB_BIT1: equ 1 ; Comparator B High Compare Bit 1
DBGCB_BIT2: equ 2 ; Comparator B High Compare Bit 2
DBGCB_BIT3: equ 3 ; Comparator B High Compare Bit 3
DBGCB_BIT4: equ 4 ; Comparator B High Compare Bit 4
DBGCB_BIT5: equ 5 ; Comparator B High Compare Bit 5
DBGCB_BIT6: equ 6 ; Comparator B High Compare Bit 6
DBGCB_BIT7: equ 7 ; Comparator B High Compare Bit 7
DBGCB_BIT8: equ 8 ; Comparator B High Compare Bit 8
DBGCB_BIT9: equ 9 ; Comparator B High Compare Bit 9
DBGCB_BIT10: equ 10 ; Comparator B High Compare Bit 10
DBGCB_BIT11: equ 11 ; Comparator B High Compare Bit 11
DBGCB_BIT12: equ 12 ; Comparator B High Compare Bit 12
DBGCB_BIT13: equ 13 ; Comparator B High Compare Bit 13
DBGCB_BIT14: equ 14 ; Comparator B High Compare Bit 14
DBGCB_BIT15: equ 15 ; Comparator B High Compare Bit 15
; bit position masks
mDBGCB_BIT0: equ %00000001
mDBGCB_BIT1: equ %00000010
mDBGCB_BIT2: equ %00000100
mDBGCB_BIT3: equ %00001000
mDBGCB_BIT4: equ %00010000
mDBGCB_BIT5: equ %00100000
mDBGCB_BIT6: equ %01000000
mDBGCB_BIT7: equ %10000000
mDBGCB_BIT8: equ %100000000
mDBGCB_BIT9: equ %1000000000
mDBGCB_BIT10: equ %10000000000
mDBGCB_BIT11: equ %100000000000
mDBGCB_BIT12: equ %1000000000000
mDBGCB_BIT13: equ %10000000000000
mDBGCB_BIT14: equ %100000000000000
mDBGCB_BIT15: equ %1000000000000000
;*** DBGCBH - Debug Comparator B Register High; 0x0000002E ***
DBGCBH: equ $0000002E ;*** DBGCBH - Debug Comparator B Register High; 0x0000002E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCBH_BIT8: equ 0 ; Comparator B High Compare Bit 8
DBGCBH_BIT9: equ 1 ; Comparator B High Compare Bit 9
DBGCBH_BIT10: equ 2 ; Comparator B High Compare Bit 10
DBGCBH_BIT11: equ 3 ; Comparator B High Compare Bit 11
DBGCBH_BIT12: equ 4 ; Comparator B High Compare Bit 12
DBGCBH_BIT13: equ 5 ; Comparator B High Compare Bit 13
DBGCBH_BIT14: equ 6 ; Comparator B High Compare Bit 14
DBGCBH_BIT15: equ 7 ; Comparator B High Compare Bit 15
; bit position masks
mDBGCBH_BIT8: equ %00000001
mDBGCBH_BIT9: equ %00000010
mDBGCBH_BIT10: equ %00000100
mDBGCBH_BIT11: equ %00001000
mDBGCBH_BIT12: equ %00010000
mDBGCBH_BIT13: equ %00100000
mDBGCBH_BIT14: equ %01000000
mDBGCBH_BIT15: equ %10000000
;*** DBGCBL - Debug Comparator B Register Low; 0x0000002F ***
DBGCBL: equ $0000002F ;*** DBGCBL - Debug Comparator B Register Low; 0x0000002F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DBGCBL_BIT0: equ 0 ; Comparator B High Compare Bit 0
DBGCBL_BIT1: equ 1 ; Comparator B High Compare Bit 1
DBGCBL_BIT2: equ 2 ; Comparator B High Compare Bit 2
DBGCBL_BIT3: equ 3 ; Comparator B High Compare Bit 3
DBGCBL_BIT4: equ 4 ; Comparator B High Compare Bit 4
DBGCBL_BIT5: equ 5 ; Comparator B High Compare Bit 5
DBGCBL_BIT6: equ 6 ; Comparator B High Compare Bit 6
DBGCBL_BIT7: equ 7 ; Comparator B High Compare Bit 7
; bit position masks
mDBGCBL_BIT0: equ %00000001
mDBGCBL_BIT1: equ %00000010
mDBGCBL_BIT2: equ %00000100
mDBGCBL_BIT3: equ %00001000
mDBGCBL_BIT4: equ %00010000
mDBGCBL_BIT5: equ %00100000
mDBGCBL_BIT6: equ %01000000
mDBGCBL_BIT7: equ %10000000
;*** PPAGE - Page Index Register; 0x00000030 ***
PPAGE: equ $00000030 ;*** PPAGE - Page Index Register; 0x00000030 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PPAGE_PIX0: equ 0 ; Page Index Register Bit 0
PPAGE_PIX1: equ 1 ; Page Index Register Bit 1
PPAGE_PIX2: equ 2 ; Page Index Register Bit 2
PPAGE_PIX3: equ 3 ; Page Index Register Bit 3
PPAGE_PIX4: equ 4 ; Page Index Register Bit 4
PPAGE_PIX5: equ 5 ; Page Index Register Bit 5
; bit position masks
mPPAGE_PIX0: equ %00000001
mPPAGE_PIX1: equ %00000010
mPPAGE_PIX2: equ %00000100
mPPAGE_PIX3: equ %00001000
mPPAGE_PIX4: equ %00010000
mPPAGE_PIX5: equ %00100000
;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
SYNR: equ $00000034 ;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SYNR_SYN0: equ 0 ; CRG Synthesizer Bit 0
SYNR_SYN1: equ 1 ; CRG Synthesizer Bit 1
SYNR_SYN2: equ 2 ; CRG Synthesizer Bit 2
SYNR_SYN3: equ 3 ; CRG Synthesizer Bit 3
SYNR_SYN4: equ 4 ; CRG Synthesizer Bit 4
SYNR_SYN5: equ 5 ; CRG Synthesizer Bit 5
; bit position masks
mSYNR_SYN0: equ %00000001
mSYNR_SYN1: equ %00000010
mSYNR_SYN2: equ %00000100
mSYNR_SYN3: equ %00001000
mSYNR_SYN4: equ %00010000
mSYNR_SYN5: equ %00100000
;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
REFDV: equ $00000035 ;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
REFDV_REFDV0: equ 0 ; CRG Reference Divider Bit 0
REFDV_REFDV1: equ 1 ; CRG Reference Divider Bit 1
REFDV_REFDV2: equ 2 ; CRG Reference Divider Bit 2
REFDV_REFDV3: equ 3 ; CRG Reference Divider Bit 3
; bit position masks
mREFDV_REFDV0: equ %00000001
mREFDV_REFDV1: equ %00000010
mREFDV_REFDV2: equ %00000100
mREFDV_REFDV3: equ %00001000
;*** CRGFLG - CRG Flags Register; 0x00000037 ***
CRGFLG: equ $00000037 ;*** CRGFLG - CRG Flags Register; 0x00000037 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CRGFLG_SCM: equ 0 ; Self-clock mode Status
CRGFLG_SCMIF: equ 1 ; Self-clock mode Interrupt Flag
CRGFLG_TRACK: equ 2 ; Track Status
CRGFLG_LOCK: equ 3 ; Lock Status
CRGFLG_LOCKIF: equ 4 ; PLL Lock Interrupt Flag
CRGFLG_LVRF: equ 5 ; Self-clock mode Status
CRGFLG_PORF: equ 6 ; Power on Reset Flag
CRGFLG_RTIF: equ 7 ; Real Time Interrupt Flag
; bit position masks
mCRGFLG_SCM: equ %00000001
mCRGFLG_SCMIF: equ %00000010
mCRGFLG_TRACK: equ %00000100
mCRGFLG_LOCK: equ %00001000
mCRGFLG_LOCKIF: equ %00010000
mCRGFLG_LVRF: equ %00100000
mCRGFLG_PORF: equ %01000000
mCRGFLG_RTIF: equ %10000000
;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
CRGINT: equ $00000038 ;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CRGINT_SCMIE: equ 1 ; Self-clock mode Interrupt Enable
CRGINT_LOCKIE: equ 4 ; Lock Interrupt Enable
CRGINT_RTIE: equ 7 ; Real Time Interrupt Enable
; bit position masks
mCRGINT_SCMIE: equ %00000010
mCRGINT_LOCKIE: equ %00010000
mCRGINT_RTIE: equ %10000000
;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
CLKSEL: equ $00000039 ;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CLKSEL_COPWAI: equ 0 ; COP stops in WAIT mode
CLKSEL_RTIWAI: equ 1 ; RTI stops in WAIT mode
CLKSEL_CWAI: equ 2 ; CLK24 and CLK23 stop in WAIT mode
CLKSEL_PLLWAI: equ 3 ; PLL stops in WAIT mode
CLKSEL_ROAWAI: equ 4 ; Reduced Oscillator Amplitude in WAIT mode
CLKSEL_SYSWAI: equ 5 ; System clocks stop in WAIT mode
CLKSEL_PSTP: equ 6 ; Pseudo Stop
CLKSEL_PLLSEL: equ 7 ; PLL selected for system clock
; bit position masks
mCLKSEL_COPWAI: equ %00000001
mCLKSEL_RTIWAI: equ %00000010
mCLKSEL_CWAI: equ %00000100
mCLKSEL_PLLWAI: equ %00001000
mCLKSEL_ROAWAI: equ %00010000
mCLKSEL_SYSWAI: equ %00100000
mCLKSEL_PSTP: equ %01000000
mCLKSEL_PLLSEL: equ %10000000
;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
PLLCTL: equ $0000003A ;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PLLCTL_SCME: equ 0 ; Self-clock mode enable
PLLCTL_PCE: equ 1 ; COP Enable during Pseudo Stop Bit
PLLCTL_PRE: equ 2 ; RTI Enable during Pseudo Stop Bit
PLLCTL_ACQ: equ 4 ; Acquisition
PLLCTL_AUTO: equ 5 ; Automatic Bandwidth Control
PLLCTL_PLLON: equ 6 ; Phase Lock Loop On
PLLCTL_CME: equ 7 ; Clock Monitor Enable
; bit position masks
mPLLCTL_SCME: equ %00000001
mPLLCTL_PCE: equ %00000010
mPLLCTL_PRE: equ %00000100
mPLLCTL_ACQ: equ %00010000
mPLLCTL_AUTO: equ %00100000
mPLLCTL_PLLON: equ %01000000
mPLLCTL_CME: equ %10000000
;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
RTICTL: equ $0000003B ;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
RTICTL_RTR0: equ 0 ; Real Time Interrupt Modulus Counter Select Bit 0
RTICTL_RTR1: equ 1 ; Real Time Interrupt Modulus Counter Select Bit 1
RTICTL_RTR2: equ 2 ; Real Time Interrupt Modulus Counter Select Bit 2
RTICTL_RTR3: equ 3 ; Real Time Interrupt Modulus Counter Select Bit 3
RTICTL_RTR4: equ 4 ; Real Time Interrupt Prescale Rate Select Bit 4
RTICTL_RTR5: equ 5 ; Real Time Interrupt Prescale Rate Select Bit 5
RTICTL_RTR6: equ 6 ; Real Time Interrupt Prescale Rate Select Bit 6
; bit position masks
mRTICTL_RTR0: equ %00000001
mRTICTL_RTR1: equ %00000010
mRTICTL_RTR2: equ %00000100
mRTICTL_RTR3: equ %00001000
mRTICTL_RTR4: equ %00010000
mRTICTL_RTR5: equ %00100000
mRTICTL_RTR6: equ %01000000
;*** COPCTL - CRG COP Control Register; 0x0000003C ***
COPCTL: equ $0000003C ;*** COPCTL - CRG COP Control Register; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
COPCTL_CR0: equ 0 ; COP Watchdog Timer Rate select Bit 0
COPCTL_CR1: equ 1 ; COP Watchdog Timer Rate select Bit 1
COPCTL_CR2: equ 2 ; COP Watchdog Timer Rate select Bit 2
COPCTL_RSBCK: equ 6 ; COP and RTI stop in Active BDM mode Bit
COPCTL_WCOP: equ 7 ; Window COP mode
; bit position masks
mCOPCTL_CR0: equ %00000001
mCOPCTL_CR1: equ %00000010
mCOPCTL_CR2: equ %00000100
mCOPCTL_RSBCK: equ %01000000
mCOPCTL_WCOP: equ %10000000
;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
ARMCOP: equ $0000003F ;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ARMCOP_BIT0: equ 0 ; CRG COP Timer Arm/Reset Bit 0
ARMCOP_BIT1: equ 1 ; CRG COP Timer Arm/Reset Bit 1
ARMCOP_BIT2: equ 2 ; CRG COP Timer Arm/Reset Bit 2
ARMCOP_BIT3: equ 3 ; CRG COP Timer Arm/Reset Bit 3
ARMCOP_BIT4: equ 4 ; CRG COP Timer Arm/Reset Bit 4
ARMCOP_BIT5: equ 5 ; CRG COP Timer Arm/Reset Bit 5
ARMCOP_BIT6: equ 6 ; CRG COP Timer Arm/Reset Bit 6
ARMCOP_BIT7: equ 7 ; CRG COP Timer Arm/Reset Bit 7
; bit position masks
mARMCOP_BIT0: equ %00000001
mARMCOP_BIT1: equ %00000010
mARMCOP_BIT2: equ %00000100
mARMCOP_BIT3: equ %00001000
mARMCOP_BIT4: equ %00010000
mARMCOP_BIT5: equ %00100000
mARMCOP_BIT6: equ %01000000
mARMCOP_BIT7: equ %10000000
;*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***
TIOS: equ $00000040 ;*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TIOS_IOS0: equ 0 ; Input Capture or Output Compare Channel Configuration Bit 0
TIOS_IOS1: equ 1 ; Input Capture or Output Compare Channel Configuration Bit 1
TIOS_IOS2: equ 2 ; Input Capture or Output Compare Channel Configuration Bit 2
TIOS_IOS3: equ 3 ; Input Capture or Output Compare Channel Configuration Bit 3
TIOS_IOS4: equ 4 ; Input Capture or Output Compare Channel Configuration Bit 4
TIOS_IOS5: equ 5 ; Input Capture or Output Compare Channel Configuration Bit 5
TIOS_IOS6: equ 6 ; Input Capture or Output Compare Channel Configuration Bit 6
TIOS_IOS7: equ 7 ; Input Capture or Output Compare Channel Configuration Bit 7
; bit position masks
mTIOS_IOS0: equ %00000001
mTIOS_IOS1: equ %00000010
mTIOS_IOS2: equ %00000100
mTIOS_IOS3: equ %00001000
mTIOS_IOS4: equ %00010000
mTIOS_IOS5: equ %00100000
mTIOS_IOS6: equ %01000000
mTIOS_IOS7: equ %10000000
;*** CFORC - Timer Compare Force Register; 0x00000041 ***
CFORC: equ $00000041 ;*** CFORC - Timer Compare Force Register; 0x00000041 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CFORC_FOC0: equ 0 ; Force Output Compare Action for Channel 0
CFORC_FOC1: equ 1 ; Force Output Compare Action for Channel 1
CFORC_FOC2: equ 2 ; Force Output Compare Action for Channel 2
CFORC_FOC3: equ 3 ; Force Output Compare Action for Channel 3
CFORC_FOC4: equ 4 ; Force Output Compare Action for Channel 4
CFORC_FOC5: equ 5 ; Force Output Compare Action for Channel 5
CFORC_FOC6: equ 6 ; Force Output Compare Action for Channel 6
CFORC_FOC7: equ 7 ; Force Output Compare Action for Channel 7
; bit position masks
mCFORC_FOC0: equ %00000001
mCFORC_FOC1: equ %00000010
mCFORC_FOC2: equ %00000100
mCFORC_FOC3: equ %00001000
mCFORC_FOC4: equ %00010000
mCFORC_FOC5: equ %00100000
mCFORC_FOC6: equ %01000000
mCFORC_FOC7: equ %10000000
;*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***
OC7M: equ $00000042 ;*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
OC7M_OC7M0: equ 0 ; Output Compare 7 Mask Bit 0
OC7M_OC7M1: equ 1 ; Output Compare 7 Mask Bit 1
OC7M_OC7M2: equ 2 ; Output Compare 7 Mask Bit 2
OC7M_OC7M3: equ 3 ; Output Compare 7 Mask Bit 3
OC7M_OC7M4: equ 4 ; Output Compare 7 Mask Bit 4
OC7M_OC7M5: equ 5 ; Output Compare 7 Mask Bit 5
OC7M_OC7M6: equ 6 ; Output Compare 7 Mask Bit 6
OC7M_OC7M7: equ 7 ; Output Compare 7 Mask Bit 7
; bit position masks
mOC7M_OC7M0: equ %00000001
mOC7M_OC7M1: equ %00000010
mOC7M_OC7M2: equ %00000100
mOC7M_OC7M3: equ %00001000
mOC7M_OC7M4: equ %00010000
mOC7M_OC7M5: equ %00100000
mOC7M_OC7M6: equ %01000000
mOC7M_OC7M7: equ %10000000
;*** OC7D - Output Compare 7 Data Register; 0x00000043 ***
OC7D: equ $00000043 ;*** OC7D - Output Compare 7 Data Register; 0x00000043 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
OC7D_OC7D0: equ 0 ; Output Compare 7 Bit 0
OC7D_OC7D1: equ 1 ; Output Compare 7 Bit 1
OC7D_OC7D2: equ 2 ; Output Compare 7 Bit 2
OC7D_OC7D3: equ 3 ; Output Compare 7 Bit 3
OC7D_OC7D4: equ 4 ; Output Compare 7 Bit 4
OC7D_OC7D5: equ 5 ; Output Compare 7 Bit 5
OC7D_OC7D6: equ 6 ; Output Compare 7 Bit 6
OC7D_OC7D7: equ 7 ; Output Compare 7 Bit 7
; bit position masks
mOC7D_OC7D0: equ %00000001
mOC7D_OC7D1: equ %00000010
mOC7D_OC7D2: equ %00000100
mOC7D_OC7D3: equ %00001000
mOC7D_OC7D4: equ %00010000
mOC7D_OC7D5: equ %00100000
mOC7D_OC7D6: equ %01000000
mOC7D_OC7D7: equ %10000000
;*** TCNT - Timer Count Register; 0x00000044 ***
TCNT: equ $00000044 ;*** TCNT - Timer Count Register; 0x00000044 ***
;*** TCNTHi - Timer Count Register High; 0x00000044 ***
TCNTHi: equ $00000044 ;*** TCNTHi - Timer Count Register High; 0x00000044 ***
;*** TCNTLo - Timer Count Register Low; 0x00000045 ***
TCNTLo: equ $00000045 ;*** TCNTLo - Timer Count Register Low; 0x00000045 ***
;*** TSCR1 - Timer System Control Register1; 0x00000046 ***
TSCR1: equ $00000046 ;*** TSCR1 - Timer System Control Register1; 0x00000046 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TSCR1_TFFCA: equ 4 ; Timer Fast Flag Clear All
TSCR1_TSFRZ: equ 5 ; Timer and Modulus Counter Stop While in Freeze Mode
TSCR1_TSWAI: equ 6 ; Timer Module Stops While in Wait
TSCR1_TEN: equ 7 ; Timer Enable
; bit position masks
mTSCR1_TFFCA: equ %00010000
mTSCR1_TSFRZ: equ %00100000
mTSCR1_TSWAI: equ %01000000
mTSCR1_TEN: equ %10000000
;*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***
TTOV: equ $00000047 ;*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TTOV_TOV0: equ 0 ; Toggle On Overflow Bit 0
TTOV_TOV1: equ 1 ; Toggle On Overflow Bit 1
TTOV_TOV2: equ 2 ; Toggle On Overflow Bit 2
TTOV_TOV3: equ 3 ; Toggle On Overflow Bit 3
TTOV_TOV4: equ 4 ; Toggle On Overflow Bit 4
TTOV_TOV5: equ 5 ; Toggle On Overflow Bit 5
TTOV_TOV6: equ 6 ; Toggle On Overflow Bit 6
TTOV_TOV7: equ 7 ; Toggle On Overflow Bit 7
; bit position masks
mTTOV_TOV0: equ %00000001
mTTOV_TOV1: equ %00000010
mTTOV_TOV2: equ %00000100
mTTOV_TOV3: equ %00001000
mTTOV_TOV4: equ %00010000
mTTOV_TOV5: equ %00100000
mTTOV_TOV6: equ %01000000
mTTOV_TOV7: equ %10000000
;*** TCTL1 - Timer Control Register 1; 0x00000048 ***
TCTL1: equ $00000048 ;*** TCTL1 - Timer Control Register 1; 0x00000048 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TCTL1_OL4: equ 0 ; Output Level Bit 4
TCTL1_OM4: equ 1 ; Output Mode Bit 4
TCTL1_OL5: equ 2 ; Output Level Bit 5
TCTL1_OM5: equ 3 ; Output Mode Bit 5
TCTL1_OL6: equ 4 ; Output Level Bit 6
TCTL1_OM6: equ 5 ; Output Mode Bit 6
TCTL1_OL7: equ 6 ; Output Level Bit 7
TCTL1_OM7: equ 7 ; Output Mode Bit 7
; bit position masks
mTCTL1_OL4: equ %00000001
mTCTL1_OM4: equ %00000010
mTCTL1_OL5: equ %00000100
mTCTL1_OM5: equ %00001000
mTCTL1_OL6: equ %00010000
mTCTL1_OM6: equ %00100000
mTCTL1_OL7: equ %01000000
mTCTL1_OM7: equ %10000000
;*** TCTL2 - Timer Control Register 2; 0x00000049 ***
TCTL2: equ $00000049 ;*** TCTL2 - Timer Control Register 2; 0x00000049 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TCTL2_OL0: equ 0 ; Output Level Bit 0
TCTL2_OM0: equ 1 ; Output Mode Bit 0
TCTL2_OL1: equ 2 ; Output Level Bit 1
TCTL2_OM1: equ 3 ; Output Mode Bit 1
TCTL2_OL2: equ 4 ; Output Level Bit 2
TCTL2_OM2: equ 5 ; Output Mode Bit 2
TCTL2_OL3: equ 6 ; Output Level Bit 3
TCTL2_OM3: equ 7 ; Output Mode Bit 3
; bit position masks
mTCTL2_OL0: equ %00000001
mTCTL2_OM0: equ %00000010
mTCTL2_OL1: equ %00000100
mTCTL2_OM1: equ %00001000
mTCTL2_OL2: equ %00010000
mTCTL2_OM2: equ %00100000
mTCTL2_OL3: equ %01000000
mTCTL2_OM3: equ %10000000
;*** TCTL3 - Timer Control Register 3; 0x0000004A ***
TCTL3: equ $0000004A ;*** TCTL3 - Timer Control Register 3; 0x0000004A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TCTL3_EDG4A: equ 0 ; Input Capture Edge Control 4A
TCTL3_EDG4B: equ 1 ; Input Capture Edge Control 4B
TCTL3_EDG5A: equ 2 ; Input Capture Edge Control 5A
TCTL3_EDG5B: equ 3 ; Input Capture Edge Control 5B
TCTL3_EDG6A: equ 4 ; Input Capture Edge Control 6A
TCTL3_EDG6B: equ 5 ; Input Capture Edge Control 6B
TCTL3_EDG7A: equ 6 ; Input Capture Edge Control 7A
TCTL3_EDG7B: equ 7 ; Input Capture Edge Control 7B
; bit position masks
mTCTL3_EDG4A: equ %00000001
mTCTL3_EDG4B: equ %00000010
mTCTL3_EDG5A: equ %00000100
mTCTL3_EDG5B: equ %00001000
mTCTL3_EDG6A: equ %00010000
mTCTL3_EDG6B: equ %00100000
mTCTL3_EDG7A: equ %01000000
mTCTL3_EDG7B: equ %10000000
;*** TCTL4 - Timer Control Register 4; 0x0000004B ***
TCTL4: equ $0000004B ;*** TCTL4 - Timer Control Register 4; 0x0000004B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TCTL4_EDG0A: equ 0 ; Input Capture Edge Control 0A
TCTL4_EDG0B: equ 1 ; Input Capture Edge Control 0B
TCTL4_EDG1A: equ 2 ; Input Capture Edge Control 1A
TCTL4_EDG1B: equ 3 ; Input Capture Edge Control 1B
TCTL4_EDG2A: equ 4 ; Input Capture Edge Control 2A
TCTL4_EDG2B: equ 5 ; Input Capture Edge Control 2B
TCTL4_EDG3A: equ 6 ; Input Capture Edge Control 3A
TCTL4_EDG3B: equ 7 ; Input Capture Edge Control 3B
; bit position masks
mTCTL4_EDG0A: equ %00000001
mTCTL4_EDG0B: equ %00000010
mTCTL4_EDG1A: equ %00000100
mTCTL4_EDG1B: equ %00001000
mTCTL4_EDG2A: equ %00010000
mTCTL4_EDG2B: equ %00100000
mTCTL4_EDG3A: equ %01000000
mTCTL4_EDG3B: equ %10000000
;*** TIE - Timer Interrupt Enable Register; 0x0000004C ***
TIE: equ $0000004C ;*** TIE - Timer Interrupt Enable Register; 0x0000004C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TIE_C0I: equ 0 ; Input Capture/Output Compare Interrupt Enable Bit 0
TIE_C1I: equ 1 ; Input Capture/Output Compare Interrupt Enable Bit 1
TIE_C2I: equ 2 ; Input Capture/Output Compare Interrupt Enable Bit 2
TIE_C3I: equ 3 ; Input Capture/Output Compare Interrupt Enable Bit 3
TIE_C4I: equ 4 ; Input Capture/Output Compare Interrupt Enable Bit 4
TIE_C5I: equ 5 ; Input Capture/Output Compare Interrupt Enable Bit 5
TIE_C6I: equ 6 ; Input Capture/Output Compare Interrupt Enable Bit 6
TIE_C7I: equ 7 ; Input Capture/Output Compare Interrupt Enable Bit 7
; bit position masks
mTIE_C0I: equ %00000001
mTIE_C1I: equ %00000010
mTIE_C2I: equ %00000100
mTIE_C3I: equ %00001000
mTIE_C4I: equ %00010000
mTIE_C5I: equ %00100000
mTIE_C6I: equ %01000000
mTIE_C7I: equ %10000000
;*** TSCR2 - Timer System Control Register 2; 0x0000004D ***
TSCR2: equ $0000004D ;*** TSCR2 - Timer System Control Register 2; 0x0000004D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TSCR2_PR0: equ 0 ; Timer Prescaler Select Bit 0
TSCR2_PR1: equ 1 ; Timer Prescaler Select Bit 1
TSCR2_PR2: equ 2 ; Timer Prescaler Select Bit 2
TSCR2_TCRE: equ 3 ; Timer Counter Reset Enable
TSCR2_TOI: equ 7 ; Timer Overflow Interrupt Enable
; bit position masks
mTSCR2_PR0: equ %00000001
mTSCR2_PR1: equ %00000010
mTSCR2_PR2: equ %00000100
mTSCR2_TCRE: equ %00001000
mTSCR2_TOI: equ %10000000
;*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***
TFLG1: equ $0000004E ;*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TFLG1_C0F: equ 0 ; Input Capture/Output Compare Channel Flag 0
TFLG1_C1F: equ 1 ; Input Capture/Output Compare Channel Flag 1
TFLG1_C2F: equ 2 ; Input Capture/Output Compare Channel Flag 2
TFLG1_C3F: equ 3 ; Input Capture/Output Compare Channel Flag 3
TFLG1_C4F: equ 4 ; Input Capture/Output Compare Channel Flag 4
TFLG1_C5F: equ 5 ; Input Capture/Output Compare Channel Flag 5
TFLG1_C6F: equ 6 ; Input Capture/Output Compare Channel Flag 6
TFLG1_C7F: equ 7 ; Input Capture/Output Compare Channel Flag 7
; bit position masks
mTFLG1_C0F: equ %00000001
mTFLG1_C1F: equ %00000010
mTFLG1_C2F: equ %00000100
mTFLG1_C3F: equ %00001000
mTFLG1_C4F: equ %00010000
mTFLG1_C5F: equ %00100000
mTFLG1_C6F: equ %01000000
mTFLG1_C7F: ...