ECE3421 XXXXXXXXXX2022 Spring ECE3421 Lab 3 CMOS NAND Gate Design The figure below shows the schematic diagram for a NAND gate with Wn = Wp = 1.5μm, and for both NMOS and PMOS, L = 0.6μm. 1. Draw the...

Design each circuit in Cadence and answer the questions please


ECE3421 2022 Spring ECE3421 Lab 3 CMOS NAND Gate Design The figure below shows the schematic diagram for a NAND gate with Wn = Wp = 1.5μm, and for both NMOS and PMOS, L = 0.6μm. 1. Draw the schematic for this circuit on Cadence. 2. Make a symbol for this circuit. 3. To test your circuit, plot the input output characteristics. Figure 1. Schematic diagram of a NAND gate. Homework 1. Schematic for the above NAND gate. 2. Input/output waveform showing all possible inputs for A & B, and list the results in a table. Hint: can use two vpulse with a different period for A & B, then capture the simulation waveform with multiple cases. 3. What is the worst-case propagation delay and on what input line? Explain why that is the worst-case. (Hint: delay occurs at the output switching, and is measured through a 2.5V ECE3421 2022 Spring marker. Take a look at all cases, i.e. A=1, B is switching low to high. Make a table with different cases and their delay time.) 4. To balance the NAND, worst-case delays of pull-up and pull-down should be managed to the same. If NMOS mobility ideally 2 times of PMOS, the balance is just let all transistors with the same length. Actually, that ratio is a little bit different from 2, and the above transistor size is not totally balanced. Keep the length and adjust widths around 1.5μm, then demonstrate the performance difference with the original design over the worst-case delay. (Hint: kn/kp can be estimated through former lab) Last edited: 02/13/22 by Zongming Li Microsoft Word - lab5 ECE3421 Lab 5 In this lab, you will design the logic function F = A(B+C)+D (a) Design the circuit schematic of static CMOS implementation. Choose transistor sizes to balance the worst-case pull-up and pull-down delays. (b) Find a Eular path and design the corresponding layout using shared diffusions and matching your schematic transistor sizes. Submit your schematic/layout and LVS/DRC results. Microsoft Word - Document1 ECE3421 Lab 6 In this lab, you will design the logic function F = A(B+C)+D using dynamic CMOS implementation. You may re-use the NMOS part from Lab 5. Finish schematic and layout. (a) Keep A, B, and C at zero, and D has a low-to-high transition in the middle of the evaluation phase. Simulate and obtain output waveforms. (b) Keep A, B, and C at zero, and D has a high-to-low transition in the middle of the evaluation phase. Simulate and obtain output waveforms. (c) Explain whether the outputs of the above two cases generate the correct logic values or not.