Microsoft Word - Homework 3 -Fall 2022.docx2022 MAE 183B/EE 153/BE 153/ChE 153 Introduction to Microscale and Nanoscale Manufacturing Homework 3 Due date: Nov 4, 2022 (Friday) 11:59pm...

Please answer the Nanoscale manufacturing and fabrication questions attached


Microsoft Word - Homework 3 -Fall 2022.docx 2022 MAE 183B/EE 153/BE 153/ChE 153 Introduction to Microscale and Nanoscale Manufacturing Homework 3 Due date: Nov 4, 2022 (Friday) 11:59pm 1. For a photoresist, the relationship between exposure energy and thickness after development is often drawn on a semi-log plot. Therefore, it is important to learn how to accurately read the value from a log scale plot. What are the values of point A and point B on the log scale below 2. Thermal expansion mismatch between a wafer and a mask is a potential source of misalignment in the photolithography process. In your photolithography experiment, you found that point C (center of the wafer and the mask) between the wafer and mask is perfectly aligned, but point A is misaligned by 1um. Please answer the following questions. (A) How much misalignment will be measured at point B? (B) If you change the size of wafer and mask to 4”, and the center point C is also perfectly aligned, how much misalignment you should expect to have in point A? 3. The following schematic shows the standing wave effect during the photolithography process. The UV light source has a wavelength of 360nm. If the refractive index (n) of the photoresist (PR) is 1.5. What is the thickness of the photoresist? 4. Design rules and process flow (A)The foundry gives below design rules to guide your fabrication process. Please describe a process flow that can result in following square array without violating any of the design rules. Describe the step-by-step processes including the photolithography, etching, and deposition. You can assume you can use a CVD method to deposit both the polysilicon and oxide layers, and the CVD deposition provide uniform coating everywhere even at the sidewalls of the structure. The etching process is also uniform. Layer Min feature size (μm) Gap and spacing (μm) Cut in (μm) Cut out (μm) Enclosure (μm) Polysilicon 2 2 2 2 2 Oxide 2 2 2 2 2